A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS

📋 论文概要

该论文实现了一个完全集成的57-66GHz正交锁相环（PLL），采用45nm数字CMOS工艺，通过两种技术解决了毫米波PLL调谐范围不足的问题，覆盖了60GHz频段的世界联合频段。

💡 主要创新点

• 采用两种技术实现宽调谐范围：一是改进的压控振荡器（VCO）设计以克服60GHz下变容管调谐能力有限的问题，二是设计具有宽锁定范围的高频预分频器。
• 在45nm数字CMOS工艺上实现了完全集成的毫米波PLL，覆盖57-66GHz频段，满足高数据速率通信需求。

🏷 关键词

📄 原文摘要

for high-data-rate communication. Despite the large amount of research on CMOS mm-wave frequency generation, current state-of-the-art mm-wave PLLs [1-5] do not achieve a tuning range that is wide enough to cover the worldwide union of bands around 60GHz (57 to 66GHz), with some margin for process and temperature variations. Achieving a large tuning range is hampered by the limited varactor tunability at 60GHz, and the need for a high-frequency prescaler with a wide locking range. A completely integrated PLL is realized in 45nm digital CMOS, using two techniques to enable the coverage of the 57-to-66GHz band. First, the targeted band of 9GHz (plus margin for process variations) is divided in two parts, each part being covered by a separate oscillator. This relaxes the tunability requirements for each oscillator. To enable direct conversion, t

👥 作者与机构

K. Scheir1,2, G. Vandersteen2, Y. Rolain2, P. Wambacq1,2, 1

IMEC, Leuven, Belgium 2 Vrije Universiteit Brussel, Brussels, Belgium The worldwide available frequency bands around 60GHz offer new opportunities