V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with Hybrid-I/O Sense Amplifier and Segmented SubArray Architecture

📋 论文概要

本文提出了一种采用混合I/O感测放大器和分段子阵列架构的4Gb DDR3 SDRAM，在56nm工艺下实现了1.6Gb/s的数据速率，解决了高带宽需求下内存容量和功耗受限的问题。

💡 主要创新点

• 提出混合I/O感测放大器（Hybrid-I/O Sense Amplifier），在保持高速读取的同时降低功耗和面积。
• 采用分段子阵列架构（Segmented SubArray Architecture），减少位线长度和延迟，提升数据带宽和能效。

🏷 关键词

📄 原文摘要

Seok-Hun Hyun, Byung-Chul Kim, In-Chul Jeong, Seong-Young Seo, Jun-Ho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kye-Hyun Kyung, Young-Hyun Jun, Kinam Kim Samsung Electronics, Hwasung, Korea As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per channel is limited to maintain high bandwidth, making the capacity requirement difficult to meet. Another problem is that computer systems impose a limit on the supply of power since their power dissipation increases rapidly, where main memories account for roughly 15% of total power consumption. To address these issues, we design a 4Gb DDR3 SDRAM that supports a 1.2V supply voltage and 1.6Gb/s data rate. Figure 7.1.1 shows the chip architecture with eight banks, each of which has two 256Mb sub-banks separated by row-address 15. The 256Mb sub-bank controls

👥 作者与机构

Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong,