A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with Controllable Repeater and On-the-Fly Power-Cut Scheme for Low-Power and High-Speed Mobile Application

📋 论文概要

该论文提出了一种用于移动DRAM的实时功耗切断方案和可控中继器技术，实现了1.35V供电下4.3GB/s带宽的1Gb LPDDR2 DRAM，解决了高速数据传输与低功耗需求之间的矛盾。

💡 主要创新点

• 提出实时功耗切断方案，无需特殊模式即可在运行中动态降低功耗。
• 采用全局数据线可控中继器，提升高速信号完整性同时减少功耗。

🏷 关键词

📄 原文摘要

Lee, Duck Hwa Hong, Jae Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin Hong Ahn, Yong Tak Kim Hynix Semiconductor, Icheon, Korea With the advent of high-performance multi-processing demands for real-time multimedia and broadband networking in battery-based mobile systems, highspeed and low power mobile SDRAM/DDRs are becoming increasingly important. We present an on-the-fly power-cut scheme that can be applied to mobile DRAM without any special modes and a global data-line repeater scheme to reduce the data-line delay. In addition, 4b data prefetch and a ZQ calibrated output driver scheme are used to achieve 4.3GB/s/chip (1066Mb/s/pin) bandwidth with 110mW power dissipation. Figure 7.3.1 shows the architecture of 1Gb LPDDR2 SDRAM. It is composed of eight banks, each with density of 128Mb. The edge pad structure, input pads,

👥 作者与机构

Bong Hwa Jeong, Jongwon Lee, Yin Jae Lee, Tae Jin Kang, Joo Hyeon