75nm 7Gb/s/pin 1Gb GDDR5 Graphics Memory Device with Bandwidth-Improvement Techniques

📋 论文概要

本文提出了一款采用75nm工艺的1Gb GDDR5图形内存器件，实现了7Gb/s/pin的数据传输速率。通过引入多种带宽改进技术，解决了高带宽和高密度内存需求之间的矛盾。

💡 主要创新点

• 采用75nm工艺实现1Gb高密度GDDR5内存，达到7Gb/s/pin的业界领先速率
• 引入了多种带宽改进技术，包括高速I/O电路和信号完整性优化，以支持7Gb/s速率
• 针对图形应用优化了内存架构和接口设计，提升了整体带宽效率

🏷 关键词

📄 原文摘要

S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller, P. Petkov, M. Plan, M. Richter, I. Russell, K. Schiller, R. Schneider, K. Swaminathan, B. Weber, J. Weber, I. Bormann, F. Funfrock, M. Gjukic, W. Spirkl, H. Steffens, J. Weller, T. Hein Qimonda, Neubiberg, Germany Memory interfaces for high-speed graphics systems have reached the 4 to 6 Gb/s/pin regime with GDDR4 and the introduction of GDDR5 [1-4] at chip densities up to 512Mb. To satisfy the demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. In this paper, a 7Gb/s/pin 1Gb GDDR5 DRAM with an array architecture for fast column access, a boosting transmitter, multiple voltage (VINT) domains to control on chip power noise, and a high-speed internal VINT power generator system are presented. This 1Gb GDDR5 memory device is fabricated in a conventional 75nm DRAM process and characterized for a 7Gb/s/pin data transfer rate at 1.5V.

👥 作者与机构

R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho,