Single-Ended Transceiver Design Techniques for 5.33Gb/s Graphics Applications

📋 论文概要

该论文针对第五代图形DDR的高带宽需求，提出了一种单端收发器设计技术，实现了5.33Gb/s的数据传输速率。通过克服单端信令在高速下的信号完整性挑战，该技术使得低引脚数单端接口能够达到以往只有差分对才能实现的速率。

💡 主要创新点

• 提出了适用于5.33Gb/s单端信号传输的收发器电路架构，解决了高速率下的噪声和串扰问题。
• 采用了阻抗匹配和均衡技术，改善了单端通道的带宽和信号质量。

🏷 关键词

📄 原文摘要

Russell Homer1, Otto Schumacher2, Reinhold Unterricker2, Werner Kederer2 Qimonda, San Jose, CA Qimonda, Munich, Germany 1 2 Graphics processing is the driving force behind the demand for high-bandwidth DRAMs. Accelerating the pace of bandwidth improvement, fifth-generation graphics DDRs will operate at data rates up to 5.33Gb/s, and support single-ended signaling for low pin-count. A significant design challenge is to ensure proper signal transmission over single-ended wires at rates previously attainable only with differential pairs. We present single-ended transceiver design techniques for 5.33Gb/s operation. In addition to the receiver and transmitter, a CML-to-CMOS converter and an integrated serializer/levelshifter are described (Fig. 7.5.1). The circuits are fabricated in 0.13µm 1.2V CMOS. The chip area is 5.7×7.0mm2 and is housed in a quadratic BGA package with 289 balls. A single-ended-to-differential receiver is classically implemented using a differential pair whose inputs ar

👥 作者与机构

Hamid Partovi1, Karthik Gopalakrishnan1, Luca Ravezzi1,