A 1.6V 3.3Gb/s GDDR3 DRAM with Dual-Mode Phase- and Delay-Locked Loop Using Power-Noise Management with Unregulated Power Supply in 54nm CMOS

📋 论文概要

本文提出了一种用于GDDR3 DRAM的双模相位与延迟锁定环（PLL/DLL），通过电源噪声管理技术，在未稳压电源下实现低抖动和宽工作范围。该设计在1.6V电压下达到3.3Gb/s的数据速率，解决了高速DRAM中DLL对电源噪声敏感的问题。

💡 主要创新点

• 提出双模相位与延迟锁定环，结合PLL和DLL的优点，适应宽频率和电压范围。
• 采用电源噪声管理技术，允许使用未稳压电源，降低系统成本并提高抖动性能。

🏷 关键词

📄 原文摘要

Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung Hynix Semiconductor, Icheon, Korea As the speed of DRAM increases and the applications spread, DLLs for DRAM require low-jitter characteristics as well as wide operating range in frequency and voltage domains. Even though digital DLLs have improved jitter control schemes [1,2,4], it is difficult to reject the jitter of the external clock in real applications. Whether a PLL or DLL is used, it should have negative delay for phase compensation in DRAM [3]. We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a

👥 作者与机构

Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi,