A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active VMIN-Enhancing Assist Circuitry

📋 论文概要

本文在22nm三栅极CMOS工艺上实现了4.6GHz、162Mb的高性能SRAM设计。通过集成主动VMIN增强辅助电路，解决了由随机和系统器件变化引起的低电压性能下降问题，显著降低了SRAM的最小工作电压。

💡 主要创新点

• 首次在22nm三栅极工艺中集成主动VMIN增强辅助电路，有效提升低电压下SRAM的稳定性。
• 利用三栅极结构改善短沟道效应和亚阈值斜率，实现37%的器件性能提升，同时保持高密度集成。
• 通过电压缩放技术实现高性能与低功耗的平衡，支持162Mb大容量阵列在4.6GHz高速运行。

🏷 关键词

📄 原文摘要

reduced power consumption, which motivates the pursuit of high-performance at reduced operating voltages. Random and systematic device variations pose significant challenges to SRAM VMIN and low-voltage performance as technology scaling follows Moore’s law to the 22nm node. A high-performance, voltagescalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon. Tri-gate technology reduces short-channel effects (SCE) and improves subthreshold slope to provide 37% improved device performance at 0.7V. Continuous device width sizing in planar technology is replaced by combining parallel silicon fins to multiply drive current. Process-circuit co-optimization of

👥 作者与机构

Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu,

Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr Intel, Hillsboro, OR Future product applications demand increasing performance with