A 6T SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Fails That Achieves 57% Faster Read and 31% Lower Read Energy

📋 论文概要

该论文提出了一种基于载流子注入方案的6T SRAM，能够精确定位并修复故障，实现了读取速度提升57%和读取功耗降低31%。主要解决了随机变化导致的电压缩放操作裕度下降问题，特别是半选择干扰问题。

💡 主要创新点

• 提出载流子注入方案，可精确定位并修复SRAM中的故障单元。
• 通过该方案实现了57%的读取速度提升和31%的读取功耗降低。
• 有效缓解了半选择干扰问题，提高了操作裕度。

🏷 关键词

📄 原文摘要

Semiconductor Technology Academic Research Center, Yokohama, Japan 1 2 Decreasing operating margins due to random variations is a key issue for voltage scaling in SRAM technology. It is particularly severe for half-select disturb because both write and read occur at the same row. While a wordline (WL) voltage assist technique [1] does not improve half-select disturbs, a negative bitline (BL) scheme [2] or asymmetric pass gate (PG) transistor with higher VTH during read [3] can be effective for mitigating half-select disturbs. While these techniques can increase operating margins, they cannot specifically target cells to correct for random variations. VTH adjustment of cell transistors by post-process carrier injection overcomes the random VTH variation problem without design and process overhead [4-6]. Figure 13.2.1 shows the conventional method where a 6T SRAM with asymmetric PG transistor formed by electron injection solves half-select disturb issues

👥 作者与机构

Kousuke Miyaji1, Toshikazu Suzuki2, Shinji Miyano2, Ken Takeuchi1

University of Tokyo, Tokyo, Japan