A 28nm 360ps-Access-Time Two-Port SRAM with a Time-Sharing Scheme to Circumvent Read Disturbs°

📋 论文概要

该论文提出了一种采用时间共享方案的28nm双端口SRAM，通过规避读干扰实现了360ps的访问时间，解决了高速图像处理中2P-SRAM的读干扰问题。

💡 主要创新点

• 提出时间共享方案，在单时钟周期内分时操作读端口和写端口，有效规避读干扰。
• 在28nm工艺下实现了360ps的快速访问时间，满足<1ns的图像处理需求。

🏷 关键词

📄 原文摘要

growth in the market for mobile information terminals such as smart phones and tablets, the performance of image processing engines (e.g., operation speed, accuracy in digital images) has improved remarkably. In these processors, 2-port SRAM (2P-SRAM) macros [1], in which a read port and a write port are operated synchronously in a single clock cycle, are widely used. As shown in Fig. 13.4.1, since the 2P-SRAM is placed in front of large scale logic circuitry for image processing, a faster access time (e.g., <1ns) is required. In general, the read-out operation in 2P-SRAM utilizes full-swing of the single read bitline (BL), so a drastic improvement of the access time is not expected. On the other hand, the dual-port SRAM (DP-SRAM) makes use of the voltage difference

👥 作者与机构

Yuichiro Ishii1, Yasumasa Tsukamoto1, Koji Nii1,

Hidehiro Fujiwara1, Makoto Yabuuchi1, Koji Tanaka2, Shinji Tanaka1, Yasuhisa Shimazaki1 Renesas Electronics, Tokyo, Japan Renesas Electronics, Itami, Japan 1 2 With the rapid