A 14.2mW 2.55-to-3GHz Cascaded PLL with

📋 论文概要

本文提出了一种低噪声级联分数N锁相环，通过使用参考注入的整数N锁相环产生800MHz低噪声参考，结合Delta-Sigma调制器，实现了-240.3dB的FOM、255fsrms的积分抖动和-53.9dBc的最差分数杂散，功耗仅14.2mW，工作在2.55-3GHz。解决了传统分数N锁相环相位噪声性能差的问题。

💡 主要创新点

• 采用级联结构：第一级为整数N数字Bang-Bang锁相环，倍频50MHz参考生成800MHz低噪声参考，作为第二级分数N锁相环的参考输入，降低了分数N锁相环的相位噪声。
• 利用800MHz Delta-Sigma调制器实现分数分频，同时通过参考注入技术抑制量化噪声，提升了整体抖动性能。

🏷 关键词

📄 原文摘要

However, their phase noise performance is typically worse than the integer-N [4, 5, 6] counterpart due to the quantization noise of the delta-sigma modulator (DSM). In this paper, we propose a low-noise fractional-N PLL that achieves best-case figure-of-merit (FOM) of -240.3dB, rms jitter of 255fsrms and worstcase fractional spur of -53.9dBc by using an 800MHz reference generated from a low-noise reference-injected integer-N PLL. The block diagram of the proposed cascaded low-noise PLL is shown in Fig. 20.2.1. The first PLL is an integer-N digital bang-bang PLL that multiplies the 50MHz reference to 800MHz. Next is a charge-pump fractional-N PLL that further multiplies the 800MHz to 2.55 to 3GHz. The role of the first PLL is to serve as a noiseless frequency multiplier. Thus to minimize the noise that is dominated by the ring oscillator, a reference injectio

👥 作者与机构

Reference Injection, 800MHz Delta-Sigma Modulator, and 255fsrms Integrated Jitter in 0.13µm CMOS

Dongmin Park, SeongHwan Cho KAIST, Daejeon, Korea Fractional-N PLLs [1-3] are widely used due to their fine frequency resolution