A 40nm CMOS All-Digital Fractional-N Synthesizer without Requiring Calibration Frank Opteynde

📋 论文概要

本文提出了一种采用40nm CMOS工艺的全数字分数-N频率合成器，无需校准即可实现低相位噪声性能。该合成器仅包含一个LC振荡器作为模拟电路，其余部分全数字实现，解决了传统Bang-Bang全数字PLL相位噪声差的问题。

💡 主要创新点

• 提出了一种无需校准的全数字分数-N频率合成器架构，简化了系统设计。
• 采用数字方式精确测量振荡器瞬时相位，实现了低相位噪声性能。
• 在40nm CMOS工艺下实现了全数字实现，仅保留LC振荡器作为模拟电路。

🏷 关键词

📄 原文摘要

Bang-Bang all-digital PLLs [1] for applications such as digital clock multiplication have existed for a long time, but show limited phase noise performance. Pioneering recent work [2-5] has demonstrated frequency synthesizers that meet the performance requirements of wireless communications systems, while containing no analog circuits except for an LC-oscillator. In order to build an AllDigital Phase-Locked Loop (ADPLL), it is necessary to measure the oscillator’s momentary phase accurately, in a digital way, since the output phase noise at frequencies within the PLL loop bandwidth is ultimately limited by the time quantisation step Δt of this phase measurement [6]: Δt .ω [ dBc / Hz ] L = 20. log ( ) (1) 12. f osc 10 sample In [2-5], a Time-to-Digital Converter (TDC) is used to measure the oscillator’s phase with a resolution of a single inverter delay. However, this approach requires calibration of the TDC conversion gain. Previous work [2] included a

👥 作者与机构

Audax-Technologies, Leuven, Belgium