A 32nm CMOS All-Digital Reconfigurable Fractional Frequency Divider for LO Generation in Multistandard SoC Radios With On-the-Fly Interference Management

📋 论文概要

本文提出了一种32nm CMOS全数字可重构分数分频器，用于多标准SoC无线电中的本地振荡器生成。通过将VCO频率偏移至PA干扰之外，有效解决了VCO拉动问题，同时利用可重构性覆盖WiFi和WiMAX等多个频段，减少了多个VCO或分数分频器带来的复杂性和面积开销。

💡 主要创新点

• 提出全数字可重构分数分频器架构，无需多个VCO即可覆盖2.3-3.8GHz和5-5.8GHz等多个频段。
• 利用数字电路实现分数分频，对工艺和电源噪声具有鲁棒性，易于在多标准SoC中集成。
• 通过可编程分频比和模式选择，实现宽频率范围覆盖和灵活的LO生成。

🏷 关键词

📄 原文摘要

sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios. To prevent VCO pulling by the PA, fractional dividers can be used to offset the VCO frequency (fvco) with respect to the PA. Multistandard radios covering, for example, WiFi 2.4 to 2.5GHz and 5 to 5.8GHz, and WiMAX 2.3 to 2.7GHz and 3.3 to 3.8GHz, may require multiple VCOs and/or multiple fractional dividers to cover all bands [1], resulting in complexity and area overhead. This paper proposes a versatile reconfigurable fractional divider capable of covering the above standards with a single VCO with 20% tuning range. The divider is all-digital, hence scalingfriendly, and uses digital calibration to eliminate the need for filtering and areaintensive inductors. The versatility afforded by the reconfigurable fractional

👥 作者与机构

Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio,

Ashoke Ravi, Yorgos Palaskas Intel, Hillsboro, OR A VCO used in a PLL inside a wireless transceiver can be