A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

📋 论文概要

该论文提出了一款采用30nm工艺、1.2V供电的4Gb DDR4 SDRAM，实现了3.2Gb/s/pin的数据速率。通过双错误检测和PVT容忍的数据获取方案，解决了高速数据传输中的可靠性和时序问题。

💡 主要创新点

• 提出双错误检测机制，提高了数据传输的可靠性。
• 设计PVT容忍的数据获取方案，确保在不同工艺、电压和温度条件下的稳定性能。

🏷 关键词

📄 原文摘要

Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki-Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byungsick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo Sun Choi, Kyung Seok Oh Samsung Electronics, Hwasung, Korea A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open drain I/O interface, and data rate increase from 1.6 to 3.2Gb/s. To achieve high performance at low supply voltage and reduce power consumption, this work introduces new functions and describes their implementation. Data bus inversion (DBI) is employed

👥 作者与机构

Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae,