A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with Bank Group and ×4 Half-Page Architecture

📋 论文概要

该论文提出了一种采用38nm工艺的1.2V 2Gb DDR4 SDRAM，通过引入Bank Group架构、内部参考电压电平(IVREF)和预加重技术，实现了2.4Gb/s/pin的高带宽数据速率，同时保持了低功耗特性，解决了传统工作频率范围受限的问题。

💡 主要创新点

• 采用Bank Group架构，通过分组管理存储阵列，提高了并行访问效率和数据带宽。
• 引入内部参考电压电平(IVREF)技术，优化了信号判决精度，降低了噪声影响。
• 使用预加重技术对输出信号进行补偿，克服了高频传输中的信号衰减，提升了工作频率范围。
• 采用×4半页架构，进一步减小了访问粒度，提高了数据吞吐率。

🏷 关键词

📄 原文摘要

Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yongju Kim, Youngdo Hur, Yunsaing Kim, Byongtae Chung, Yongtak Kim Hynix Semiconductor, Icheon, Korea DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb D

👥 作者与机构

Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim,