Nonvolatile 3D-FPGA With Monolithically Stacked RRAM-Based Configuration Memory

📋 论文概要

本文首次实现了基于RRAM配置存储器的单片堆叠式非易失3D-FPGA，通过将配置存储器垂直集成在FPGA逻辑和路由层之上，有效减小了芯片面积并降低了功耗。

💡 主要创新点

• 首次采用RRAM作为配置存储器的单片堆叠3D-FPGA架构，实现了非易失性存储。
• 利用3D集成技术将配置存储器与逻辑层垂直堆叠，相比2D-FPGA显著减小芯片面积。
• RRAM的非易失特性降低了配置存储器的静态功耗，并提升了系统可靠性。

🏷 关键词

📄 原文摘要

area, delay, and power consumption of FPGAs relative to ASICs. In [1] it is estimated that a 3D-FPGA with the configuration memory stacked on top of the FPGA logic and routing can achieve 57% smaller die area than a baseline 2D-FPGA in 65nm CMOS technology. Motivated by these potential performance gains, several programmable logic devices with different monolithically stacked configuration memory technologies have been reported [2-4]. These memory technologies, however, require materials and/or processes that may not be compatible or scalable with CMOS processes. This paper presents the first 3D-FPGA with stacked configuration memory based on the emerging nonvolatile Resistive RAM (RRAM) technology described in [5], which is both compatible and scalable with CMOS. The architecture of the proposed 3D-FPGA is shown in Fig. 23.4.1. It consists of

👥 作者与机构

Young Yang Liauw, Zhiping Zhang, Wanki Kim, Abbas El Gamal, S. Simon Wong

Stanford University, Stanford, CA SRAM based configuration memory is the primary contributor to the large