A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with Input Skew Calibration and Enhanced Control Scheme

📋 论文概要

该论文提出了一款采用30nm工艺的1.2V 4Gb LPDDR3 SDRAM，实现了1.6Gb/s/pin的数据速率。通过输入偏斜校准和增强控制方案，解决了移动DRAM在高性能需求下的功耗与速度平衡问题。

💡 主要创新点

• 提出输入偏斜校准技术，补偿信号传输中的时序偏差，提升数据眼图裕度。
• 采用增强控制方案，优化读写操作时序，降低功耗并提高带宽利用率。

🏷 关键词

📄 原文摘要

Yonggwon Jeong, Kwang-Sook Noh, Younghoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo Sun Choi, Kyungseok Oh Samsung Electronics, Hwasung, Korea Mobile DRAM is widely adopted in battery-powered portable devices because of its low power. Recently, in mobile devices such as smart phones and tablet PCs, higher performance is required to support 3D gaming mode and high-quality video. These trends lead to consideration of higher-performance DRAMs than LPDDR2, while the power budget for DRAMs for mobile devices cannot increase. DRAMs with wide I/O or serial I/O have been reviewed as candidates for over 6.4GB/s channel bandwidth. However, wide-I/O DRAMs [1] must solve issues such as stacking yield for higher density and failure analysis modeling of system-in-package (SiP), and most serial I/Os have worse I/O power efficiency than

👥 作者与机构

Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung Bum Ko,