Over-10×-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme

📋 论文概要

本文提出了一种用于固态硬盘（SSD）的高可靠性技术，包括错误预测LDPC纠错码（ECC）和错误恢复方案。错误预测LDPC ECC可将SSD寿命延长超过10倍，而错误恢复方案能分别降低编程干扰错误率74%和数据保持错误率56%，有效解决了亚20nm闪存中浮栅耦合导致的可靠性问题。

💡 主要创新点

• 提出错误预测LDPC ECC架构，通过预测错误模式实现超过10倍的SSD寿命延长。
• 设计错误恢复方案，通过降低编程干扰和数据保持错误率（分别减少74%和56%）来提升可靠性。

🏷 关键词

📄 原文摘要

This paper presents solid-state drives (SSDs) with two high reliability techniques. First, an error-prediction (EP) low-density-parity-check (LDPC) errorcorrecting code (ECC) that realizes an over 10× extended lifetime. Second, an error-recovery (ER) scheme that decreases the program-disturb error rate and the data-retention error rate by 74% and 56%, respectively. As design rules shrink, floating gate (FG)-FG capacitive coupling among neighboring memory cells seriously degrades memory cell reliability [1]. To enhance the error-correction capability, an LDPC ECC is proposed for sub-20nm flash memories instead of the Bose-Chaudhuri-Hocquenghem (BCH) ECC [2]. In a 2b/cell memory, 3 reference voltages (Vref) are needed for the BCH (Fig. 25.2.1(a)). The conventional LDPC requires many, e.g., 21 [3], Vref to get accurate VTH information (Fig. 25.2.1(b)). The inter-cell coupling is also considered

👥 作者与机构

Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi

University of Tokyo, Tokyo, Japan