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本文针对多通道SSD控制器中需要高吞吐量纠错码（ECC）的问题，提出了一种多线程BCH编码器和解码器架构，实现了Gb/s级别的数据传输速率，解决了传统BCH解码器难以同时满足高吞吐量和强纠错能力的难题。
Solid-state drives (SSDs), built with many flash memory channels, is usually connected to the host through an advanced high-speed serial interface such as SATA III associated with a transfer rate of 6Gb/s [1-2]. However, the performance of SSD is in general determined by the throughput of the ECC blocks necessary to overcome the high error-rate [3]. The binary BCH code is widely used for the SSD due to its powerful error-correction capability. As it is hard to achieve high-throughput strong BCH decoders [4-5], multiple BCH decoders are typically on a high-performance SSD controller, leading to a significant increase of hardware complexity. This paper presents an efficient BCH encoder/decoder architecture achieving a decoding throughput of 6Gb/s. The overall architecture shown in Fig. 25.3.1 includes a single BCH decoder and a multi-threaded BCH encoder. The single BCH encoder is responsible for all the channels and services a channel at a time in a round-robin manner.
Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park
KAIST, Daejeon, Korea