⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文介绍了一款采用20nm以下工艺的64Gb MLC NAND闪存，支持533Mb/s的DDR接口，解决了高密度存储与高速数据传输之间的矛盾。通过改进的电路设计和工艺技术，实现了大容量与高性能的平衡。
Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byung-Jun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kye Hyun Kyung, Young-Ho Lim, Young-Hyun Jun Samsung Electronics, Hwasung, Korea The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, w
Daeyeal Lee, Ik Joon Chang, Sang-Yong Yoon, Joonsuc Jang,