A 283.2µW 800Mb/s/pin DLL-Based Data Self-Aligner for Through-Silicon Via (TSV) Interface

📋 论文概要

本文提出了一种基于DLL的数据自对齐器，用于通过硅通孔（TSV）接口，在283.2µW功耗下实现800Mb/s/pin的数据传输速率，解决了TSV接口中因工艺变化导致的数据时序偏差问题。

💡 主要创新点

• 采用DLL（延迟锁定环）结构实现数据自对齐，无需额外校准电路，降低了功耗和面积。
• 针对TSV接口的工艺变化，设计了低功耗、高精度的延迟控制方案，在283.2µW功耗下达到800Mb/s/pin速率。

🏷 关键词

📄 原文摘要

Dae-Han Kwon2, Jong-Ho Kang2, Yunsaing Kim2, Young-Jung Choi2, Kunwoo Park2, Byong-Tae Chung2, Chulwoo Kim1 Korea University, Seoul, Korea Hynix Semiconductor, Icheon, Korea 1 2 The process variation among 512 DRAM samples is more than 30% [1]. The performance variation of general circuits is predicted to be over 60% in 2012 [2]. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more [3], the additional power consumption can

👥 作者与机构

Hyun-Woo Lee1,2, Soo-Bin Lim1, Junyoung Song1, Ja-Beom Koo1,