A 28.3mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a +27.1dBm WCDMA CMOS Power Amplifier

📋 论文概要

该论文提出了一种PA闭环技术，用于改善WCDMA CMOS功率放大器的线性度和效率，解决了输出功率与带宽之间的折衷问题。通过集成闭环反馈，实现了+27.1dBm输出功率和28.3mW功耗。

💡 主要创新点

• 提出PA闭环结构，克服了传统前馈技术在PVT和负载变化下效果不佳的问题。
• 通过闭环反馈解决了高输出功率下带宽受限的难题，实现了线性度和效率的同时提升。

🏷 关键词

📄 原文摘要

The main challenge is to improve its power efficiency. Although many linearization and efficiency improvement techniques have been proposed, most of these techniques are based on feed-forward, which may not be effective under varying PVT and load conditions [1-3]. The bandwidth is the issue for feedback techniques such as Cartesian and polar loop. There is a severe trade-off between output power and bandwidth, since generating high output power requires many gain stages including mixers and multiple drivers, which results in a large group delay. To overcome the trade-off, we propose a PA-closed loop, where an integrated feedback directly controls the final stage of a watt-level CMOS PA, as shown in Fig. 4.6.1. Although stable feedback at RF is difficult, separate phase and amplitude

👥 作者与机构

Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi,

Yasuhiko Kuriyama, Masami Nagaoka Toshiba, Kawasaki, Japan A low-cost, fully integrated CMOS PA is attractive