ISSCC 2023
Session 1
Plenary
Innovation For the Next Decade of Compute Efficiency
AMD, Fort Collins, CO2 1.1 Introduction With high-performance computing becoming an increasingly essential part of modern life, efficiently delivering improvements in compute performance is the defining challenge for our
ISSCC 2020
Session 2
Digital Processors
AMD Chiplet Architecture for High-Performance Server and Desktop Products
AMD, Austin, TX 1 2 AMD’s “Rome” and “Matisse” are second-generation AMD Infinity Fabric-based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/$ and performance/W, targe
ISSCC 2018
Session 2
Digital Processors
"Zeppelin": An SoC for Multichip Architectures
AMD, Fort Collins, CO 1 2 Codenamed “Zeppelin”, AMD’s next-generation System-on-a-Chip (SoC) was designed for use in multiple products and packages in multiple markets, including server, mainstream PC desktop, and high-e
ISSCC 2014
Session 5
Digital Processors
Adaptive Clocking System for Improved Power Efficiency in a 28nm x86-64 Microprocessor
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consum
ISSCC 2011
Session 4
Digital Processors
40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core
AMD’s two-core Bulldozer module [1,2] implements the AMD x86-64 microarchitecture in an 11-layer 32-nm SOI HKMG technology. The 40-instruction outof-order unified integer scheduler issues up to four operations per cycle