ISSCC 2026
Session 10
Digital Circuits
A 0.008mm2 16-to-1600MHz All-Digital Fractional Divider Using AUX-DLL for Background LMS-Based DTC Calibration
Abstract An all-digital high-performance standalone fractional divider (FDIV) is presented. It leverages a robust replica-free least-mean square (LMS)-based digital-to-time converter (DTC) background calibration using a
ISSCC 2017
Session 2
Power Management
A Fully Integrated Reconfigurable Wideband Envelope-Tracking SoC for High-Bandwidth WLAN Applications in a 28nm CMOS Technology
Envelope tracking (ET) has become popular for enhancing battery life in mobile communication devices that employ high peak-to-average power ratio (PAPR) signals. Most of the published ET systems have focused either on na
ISSCC 2016
Session 2
RF & Wireless
A Complementary VCO for IoE that Achieves a 195dBc/Hz FOM and Flicker Noise Corner of 200kHz
An LC oscillator can achieve near optimal performance if the common-mode of the circuit is designed to resonate at twice the oscillation frequency [1-3]. Common-mode resonance can be accomplished with an explicit tail in
ISSCC 2015
Session 25
RF & Wireless
A VCO with Implicit Common-Mode Resonance
CMOS VCO performance metrics have not improved significantly over the last decade. Indeed, the best VCO Figure of Merit (FOM) currently reported was published by Hegazi back in 2001 [1]. That topology, shown in Fig. 25.3
ISSCC 2014
Session 3
RF & Wireless
A Noise-Cancelling Receiver with Enhanced Resilience to Harmonic Blockers
By employing two passive-mixer-based downconversion paths, the frequencytranslational noise-cancelling receiver (FTNC-RX) achieves a low noise figure and can tolerate most out-of-band blockers up to 0dBm with little perf
ISSCC 2014
Session 21
Clocking & PLLs
A Pulling Mitigation Technique for Direct-Conversion Transmitters
Despite versatility and low power consumption, direct-conversion transmitters suffer from a fundamental drawback: the local oscillator disturbance by the power amplifier, through unwanted electromagnetic or capacitive co
ISSCC 2013
Session 5
RF & Wireless
A Phase-Noise and Spur Filtering Technique Using Reciprocal-Mixing Cancellation
Recent passive-mixer-based architectures, such as [1], have shown that blockers as large as 0dBm can be tolerated without excessive gain compression. However, even in a perfectly linear receiver, reciprocal mixing of the
ISSCC 2011
Session 3
RF & Wireless
A Low-Power Process-Scalable Superheterodyne Receiver with Integrated High-Q Filters
low-IF, benefitting from a simple structure, and a high level of integration as image rejection is not a major concern, and channel selection is performed by low-frequency lowpass filters [Fig. 3.5.1(a)]. Dominated by li
ISSCC 2011
Session 21
RF & Wireless
A Low-Power Wideband Polar Transmitter for 3G Applications
of the direct upconversion type. This architecture is versatile but requires calibration of the imbalance in its quadrature branches and DC offset at its inputs, and it is vulnerable to mixer noise. We believe it consume
ISSCC 2009
Session 22
RF & Wireless
A Tunable Integrated Duplexer with 50dB Isolation in 40nm CMOS
frequency-selective filters for isolation. The stringent isolation requirements prohibit the integration of RF duplexers on silicon and particularly in CMOS technology. However, CMOS technology offers superior tuning and
ISSCC 2008
Session 10
RF & Wireless
A Low-Power WCDMA Transmitter with an Integrated Notch Filter
In a WCDMA FDD system, since the transmitter and receiver operate concurrently, the receiver is plagued by the transmitter leakage due to finite isolation of antenna duplexer. As a consequence, the transmitter noise at t