机构

Francesco Buccoleri1

3 篇 ISSCC 论文

ISSCC 2024 Session 10 Clocking & PLLs
A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
Francesco Tesolin*1, Simone Mattia Dartizio*1, Giacomo Castoro1,
Andrea Leonardo Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy Infineon Technologies, Villach, Austria *Equally Credited Authors (ECAs) 1 2 Improving the spatial resolution and reliability of target de
Francesco Buccoleri1, Michele Rossoni1, Dmytro Cherniak2, Carlo Samori
ISSCC 2023 Session 4 Clocking & PLLs
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
Giacomo Castoro*1, Simone M. Dartizio*1, Francesco Tesolin1,
Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy, 2Infineon Technologies, Villach, Austria *Equally Credited Authors (ECAs) 1 The quest of increasingly higher mobile uplink/down
Francesco Buccoleri1, Michele Rossoni1, Dmytro Cherniak2, Luca Bertule
ISSCC 2023 Session 4 Clocking & PLLs
A 76.7fs-Integrated-Jitter and -71.9dBc In-Band FractionalSpur Bang-Bang Digital PLL Based on an Inverse-ConstantSlope DTC and FCW Subtractive Dithering
Simone M. Dartizio1, Francesco Tesolin1, Giacomo Castoro1,
Luca Bertulessi1, Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy, 2Infineon Technologies, Villach, Austria 1 Ultra-low-jitter and high-spectral-purity frequency synthesizers
Francesco Buccoleri1, Luca Lanzoni1, Michele Rossoni1, Dmytro Cherniak