ISSCC 2017
Session 6
Wireline I/O
A 22.5-to-32Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in 28nm CMOS
circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received data only once per UI [1,2]. This reduces the number of front-end comparators and
ISSCC 2011
Session 8
Wireline I/O
A 1-to-6Gb/s Phase-Interpolator-Based Burst-Mode CDR in 65nm CMOS
are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for severa
ISSCC 2011
Session 20
Wireline I/O
A Pattern-Guided Adaptive Equalizer in 65nm CMOS
receivers is becoming a necessity as the data rates increase without channel improvements. Adaptive equalizers can be implemented using data-aided or non-data-aided schemes [1], with the latter requiring less area and po