ISSCC 2012
Session 24
Wireline I/O
25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-Based Optical Links in 90nm CMOS
Future high-performance computing systems require sub-2pJ/bit power efficiencies at >10Gb/s [1-2]. The best reported optical link efficiencies at these data rates are ≥2.5pJ/bit [1-4]. This paper describes two VCSEL-base
ISSCC 2012
Session 10
Digital Circuits
A 3D System Prototype of an eDRAM Cache Stacked Over Processor-Like Logic Using Through-Silicon Vias
IBM Systems and Technology Group, Fishkill, NY 1 2 3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache memory is one
ISSCC 2008
Session 22
Other
A Completely Digital On-Chip Circuit for Local–Random-Variability Measurement
Accurate characterization and measurement of local variation in threshold voltage (Vt) of closely spaced devices is essential for process optimization, yield enhancement and design of analog circuits in current technolog