ISSCC 2026
Session 17
Other
The STM32N6 Microcontroller: Enabling Intelligent Edge AI for IoT and Beyond
Abstract The STM32N6 microcontroller meets the growing need for intelligent edge devices in IoT, wearables, industrial automation, and smart home systems supporting real-time, energyefficient AI processing at the edge, r
ISSCC 2015
Session 13
RF & Wireless
A -97dBm-Sensitivity Interferer-Resilient 2.4GHz Wake-Up Receiver Using Dual-IF Multi-N-Path Architecture in 65nm CMOS
University of Lille, Lille, France 1 3 Wake-up receivers are considered as practical solutions to enable ultra-lowpower (ULP) wireless sensor nodes (WSN) in a dense environment. A low data-rate (<~50kb/s) wake-up receive
ISSCC 2014
Session 22
Data Converters
A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology
France 1 After quantization, each SAR stores its 6b word in 2 ping-pong 512-word RAMs running at 10GHz/8/2=625MHz. The total 8K words are finally read at low speed through a JTAG controller. The chip is fabricated in 28n
ISSCC 2014
Session 17
Analog Circuits
Envelope Modulator for Multimode Transmitters with AC-Coupled Multilevel Regulators
STMicroelectronics, Prague, Czech Republic, 3 Czech Technical University, Prague, Czech Republic 1 2 Modern wireless communication systems, such as high-speed uplink packet access (HSUPA) or long term evolution (LTE), em
ISSCC 2012
Session 21
Analog Circuits
A 65nm CMOS 1-to-10GHz Tunable ContinuousTime Low-pass Filter for High-Data-Rate Communications
filters are in the frequency band of 1 to 3GHz [2,4-6], targeting applications like UWB communications or hard disk drives. Nevertheless, bands much higher, of about 10GHz, are to be addressed in the near future. This pa
ISSCC 2012
Session 1
Plenary
The Role of Semiconductors in the Energy Landscape Carmelo Papa
1.0 Introduction Minimizing global consumption of electrical energy is undoubtedly one of the most important challenges facing the world today. According to Exxon Mobil Energy Outlook 2010, economic growth and technologi
ISSCC 2009
Session 14
Digital Circuits
A 1GHz Digital Channel Multiplexer for Satellite Outdoor Unit Based on a 65nm CMOS Transceiver
level and characterized for different input signal slopes, load capacitances, and process corner conditions. The extracted timing characteristics have been used as constraint to drive the digital block implementation. Ba
ISSCC 2008
Session 31
RF & Wireless
A Single-Chip WCDMA Envelope Reconstruction LDMOS PA with 130MHz Switched-Mode Power Supply
signals and generally use low-efficiency linear power amplifiers. Envelope reconstruction (ER) polar architecture allows linear amplification with high efficiency, since the RF phase signal is amplified by a saturated PA
ISSCC 2008
Session 16
Digital Circuits
A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling SatelliteTransmission Portable Devices
Services compliant 2nd Generation Satellite Digital Video Broadcast (DVB-S2) [1] codec is presented. Previously published silicon implementations respecting this stringent standard reports power consumption between 800mW
ISSCC 2008
Session 12
Data Converters
A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS
Applications using broadband digital wireless modulation require high-resolution low-power ADC over a bandwidth of few megahertz. For a WiFi or a WiMAX standard, an ADC of ~10b resolution in 5 to 20MHz bandwidth is neede