ISSCC 2026
Session 7
Image Sensors
A Fully Reconfigurable Hybrid SPAD Vision Sensor with 134dB Dynamic Range Using Time-Coded Dual Exposures
Abstract This paper presents a fully reconfigurable HDR intensity/event hybrid SPAD sensor. The fully reconfigurable scheme enables both pixel types to be freely blended and operated simultaneously. A time-coded dual exp
ISSCC 2026
Session 2
Digital Processors
A 71.3mJ/Frame End-to-End Driving Processor with Flexible Heterogeneous Core Orchestration via Sparsity Reasoning
*Equally Credited Authors (ECAs) 1 Abstract A multi-modal end-to-end driving processor is proposed with 4 features: 1) a sparsity reasoning unit to maximize sparsity exploitation, 2) a flexible sparse-dense heterogeneous
ISSCC 2025
Session 15
AI / ML
A 4.6µW 3.3-NEF Biopotential Amplifier with 133VPP Common-Mode Interference Tolerance and 102dB Total Common-Mode Rejection Ratio for Two-Electrode Recording System
crucial in delivering vital information for medical diagnostics and research applications. Recently, the demand for biopotential recording using two electrodes has grown thanks to its better user experience and lower cos
ISSCC 2024
Session 6
Image Sensors
A 160×120 Flash LiDAR Sensor with Fully Analog-Assisted InPixel Histogramming TDC Based on Self-Referenced SAR ADC
surrounding objects plays a crucial role in realizing the metaverse and spatial computing on mobile devices. A LiDAR sensor based on direct time-of-flight (dToF) technology is one of the strong candidates to provide depth
ISSCC 2021
Session 7
Image Sensors
A 48×40 13.5mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital Converter
diverse applications such as user identification, interactive user interfaces with AR/VR devices, and self-driving cars. Direct time-of-flight (D-ToF) systems, LiDAR sensors, are desirable for long-distance measurements
ISSCC 2019
Session 30
Wireline I/O
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCOBased Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator
generate low-jitter high-frequency signals, while using a ring VCO. In the sense that the VCO jitter is removed periodically by the reference clock, SREF, an MDLL also can be considered to be an ILCM. However, the most c
ISSCC 2018
Session 25
Wireline I/O
A -242dB FOM and -75dBc-Reference-Spur Ring-DCO-Based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC
To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phaseerror correction (FPEC) technique [1] is one promising
ISSCC 2017
Session 19
Clocking & PLLs
A PVT-Robust -39dBc 1kHz-to-100MHz IntegratedPhase-Noise 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop Using the Averages of Phase Deviations for mm-Band 5G Transceivers
have an ultra-wide bandwidth in a mm-wave band. A big challenge of a 5G transceiver is to generate ultra-low-PN (phase noise) local-oscillator (LO) signals to suppress integrated PN (IPN) over such an extremely wide band
ISSCC 2016
Session 10
Wireline I/O
A 185fsrms-Integrated-Jitter and -245dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous FrequencyTracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector
An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption. However, an