ISSCC 2020
Session 22
Memory
A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor
Single-ended transceivers that can deliver high-data rates at reduced supply voltages are required to meet the ever-growing demands of future memory interfaces. The performance of conventional non-return-to-zero (NRZ) li
ISSCC 2019
Session 2
AI / ML
A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control
Single-source shortest path (SSP) problems have a rich history of algorithm development [1-3]. SSP has many applications including AI decision making, robot navigation, VLSI signal routing, autonomous vehicles and many o
ISSCC 2016
Session 19
Digital Circuits
A 0.2-to-1.45GHz Subsampling Fractional-N AllDigital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection
Multiplying delay-locked loops (MDLLs) are gaining popularity due to their superior noise performance over conventional phase-locked loops (PLLs) [1,2]. Recent designs are trending towards an all-digital implementation t
ISSCC 2011
Session 15
Digital Processors
A Programmable Adaptive Phase-Shifting PLL for Clock Data Compensation Under Resonant Supply Noise
Power supply noise has become one of the main performance-limiting factors in sub-1V technologies. Resonant supply noise caused by the package/bonding inductance and on-die capacitance has been reported as the dominant s
ISSCC 2009
Session 29
mm-Wave
A Dual-Mode Architecture for a Phased-Array Receiver Based on Injection Locking in 0.13µm CMOS
Phased arrays have long been used by the military for radar applications, but have only been recently applied to consumer applications. In a phased array system, one or more narrow beams are generated by transmitting (or