ISSCC 2018
Session 15
RF & Wireless
A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FOM of -246dB for IoT Applications in 65nm CMOS
ultra-lowpower (ULP) transceivers (TRX) will be key elements in a variety of short-range network applications. The RF PLL in a TRX needs a significant amount of power due to the phase noise and spurious requirement. Comp
ISSCC 2017
Session 8
Digital Circuits
A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO
(ILPLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core l
ISSCC 2014
Session 22
Data Converters
A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with Resistively Averaged Voltage-to-Time Amplifiers
as 60GHz receivers, serial links, and high-density disk drive systems. Flash architectures have the highest conversion rate without employing time interleaving. Moreover, flash architectures have the lowest latency, whic
ISSCC 2013
Session 14
Digital Circuits
A 0.022mm2 970μW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits
include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [12], subharmonically injection-locked techniques [3], and sub-sampli