机构

Northwestern University

8 篇 ISSCC 论文

ISSCC 2026 Session 36 AI / ML
A Neural Interface SoC for Smart Glasses with Low-Power Neural Commanding and Efficient LoRA-Enabled On-Chip Learning
Zhiwei Zhong*1, He Yu*1, William McGarry1, Yijie Wei2, Jie Gu1
*Equally Credited Authors (ECAs) 1 Abstract This work presents a 65nm ExG SoC for smart glasses, enabling low-power neural interaction. A 10-ch AFE and on-chip CNN deliver real-time EOG/EMG/EEG inference. Ondevice contin
Northwestern University, Evanston, IL, 2Texas Instruments, Dallas, TX
ISSCC 2026 Session 10 Digital Circuits
Proactive Power Management-Based Supply Regulation with Online Learning for Variation-Tolerant Workload-Aware Droop Mitigation in 28nm CMOS
Xi Chen1, Andrew Liss1, William Covington1, Qiankai Cao1, Yiqi Li1, Kang Wei2, Raveesh Magod3, Muhammad Khellah4, Xin Zh
IBM T. J. Watson Research Center, Yorktown Heights, NY 1 5 Abstract A 28nm SoC solution with integrated proactive power management for droop mitigation is demonstrated combining a neural droop management unit, integrated
Northwestern University, Evanston, IL, 2Texas Instruments, Dallas, TX,
ISSCC 2024 Session 33 AI / ML
A Sub-1µJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture
Zhiwei Zhong*, Yijie Wei*, Lance Christopher Go, Jie Gu
*Equally Credited Authors (ECAs) Virtual Reality (VR) and Mixed Reality (MR) systems, e.g., Meta Quest and Apple Vision Pro, have recently gained significant interest in consumer electronics, creating a new wave of develo
Northwestern University, Evanston, IL
ISSCC 2024 Session 20 AI / ML
A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices
Yuhao Ju, Ganqi Xu, Jie Gu
The demand for real-time computing on edge devices from emerging applications, e.g. AI, has exploded in recent years. Lately, physics-based scientific computing has also drawn significant interests driven by the growth of
Northwestern University, Evanston, IL
ISSCC 2024 Session 2 Digital Processors
A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices
Shiyu Guo1, Sachin Sapatnekar2, Jie Gu1
University of Minnesota, Minneapolis, MN includes a sub-group of user-defined objects inside. After the BBOX Intersection Evaluator (BBIE) detects intersection with TBBOX, the Triangle Mesh Intersection Evaluator (TIE) co
Northwestern University, Evanston, IL
ISSCC 2020 Session 31 Digital Circuits
A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators
Tianyu Jia, Yuhao Ju, Jie Gu
Dynamic timing error detection and correction techniques, e.g. razor flops, have been previously applied to microprocessors to exploit the dynamic timing margin within pipelines [1]. Adaptive clock techniques have also b
Northwestern University, Evanston, IL
ISSCC 2019 Session 19 Digital Circuits
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput
Zhengyu Chen, Jie Gu
Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW
Northwestern University, Evanston, IL
ISSCC 2019 Session 19 Digital Circuits
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GeneralPurpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution
Tianyu Jia, Russ Joseph, Jie Gu
Cycle-by-cycle dynamic timing slack (DTS), which represents extra timing margin from the critical-path timing slack reported by the static timing analysis (STA), has been observed at both program level and instruction le
Northwestern University, Evanston, IL