ISSCC 2026
Session 3
Wireless
A Near-Field RF Reflection Transceiver ASIC for Continuous Unobtrusive Blood Pressure Monitoring
Abstract This work presents continuous, unobtrusive, and clinically accurate BP monitoring in a fully wearable form factor using an near-field RF reflection TRx ASIC in 65nm CMOS. The NRR approach enables noncontact moni
ISSCC 2026
Session 20
RF & Wireless
A mm-Wave Doherty Power Amplifier in a Single-Path Footprint Using Compact Reciprocal Doherty Networks
Abstract This paper presents a compact, single-path-footprint Doherty PA with minimized passive network areas. A systematic analysis for its realization is developed based on the proposed theory of reciprocal Doherty net
ISSCC 2025
Session 5
RF & Wireless
A Blocker-Tolerant mm-Wave Low-Noise Amplifier Utilizing Doherty Active Load Modulation for Linearity Enhancement
Conventionally, the linearity of receivers (RXs) or low-noise amplifiers (LNAs) has not been a primary design focus, as they are generally optimized for handling weak input signals. However, emerging applications such as
ISSCC 2024
Session 33
AI / ML
A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend
Meta, Santa Clara, CA 3 Michigan State University, East Lansing, MI 1 2 Neural interface implants are revolutionizing neuroscience research, especially in brainmachine interfaces and neuromodulation therapies. Miniaturiz
ISSCC 2024
Session 30
AI / ML
Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing
Vector processors have re-emerged in high-performance computing and flagship mobile SoC designs for their improved programmability, appealing power efficiency over multicore processors and area efficiency over GPUs [1]. For
ISSCC 2021
Session 27
Data Converters
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
Tsinghua University, Beijing, China 1 2 Many applications, such as multi-standard wireless and event-driven IoT devices, demand high-resolution ADCs with scalable sampling rate and power consumption. The conventional pip
ISSCC 2021
Session 23
AI / ML
270-to-300GHz Double-Balanced Parametric Upconverter Using Asymmetric MOS Varactors and a Power-SplittingTransformer Hybrid in 65nm CMOS
Oklahoma State University, Stillwater, OK 1 2 Wireless communication at ~300GHz is drawing attention due to its potential to support a high data-rate using the wide available bandwidth. Transmitters operating at ~300GHz
ISSCC 2021
Session 16
AI / ML
eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing
has led to massive amounts of data movement from off-chip memory to on-chip processing cores in modern machine learning (ML) accelerators. Compute-in-memory (CIM) designs performing analog DNN computations within a memor
ISSCC 2019
Session 14
AI / ML
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing
Convolutional Neural Networks (CNN) provide superior classification accuracy in a variety of machine learning applications, such as image/speech/sensor data processing. However, CNNs require intensive compute and memory r
ISSCC 2018
Session 14
Data Converters
A 13-ENOB 2nd-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using an Error-Feedback Structure
The noise-shaping (NS) SAR ADC is an emerging hybrid architecture that achieves high resolution and power-efficiency simultaneously by combining the merits of the SAR ADC and the ΔΣADC, making it attractive to sensor rea
ISSCC 2016
Session 15
Data Converters
A 24.7mW 45MHz-BW 75.3dB-SNDR SARAssisted CT ΔΣ Modulator with 2nd-Order Noise Coupling in 65nm CMOS
Technology advancement has recently made it attractive to replace the flash quantizer (QTZ) in a multibit ΔΣ modulator by an asynchronous successiveapproximation-register (ASAR) QTZ to improve the overall power efficienc
ISSCC 2016
Session 12
Power Management
A 2MHz 12-to-100V 90%-Efficiency SelfBalancing ZVS Three-Level DC-DC Regulator with Constant-Frequency AOT V2 Control and 5ns ZVS Turn-On Delay
Wide input rails (12V to 100V) are common in today’s automotive and industrial systems. Miniaturized DC-DC voltage regulators (VRs), which can provide a lowvoltage regulated output from a wide input range and deliver a f
ISSCC 2014
Session 4
Power Management
A 6A 40MHz Four-Phase ZDS Hysteretic DC-DC Converter with 118mV Droop and 230ns Response Time for a 5A/5ns Load Transient
In recent years, the clock frequency, the number of cores, and the power dissipation of application processors (APs) for portable electronics have dramatically increased. As a result, peak processor currents have reached