ISSCC 2025
Session 13
Other
A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost
Growing interest in healthcare has led to the development of many wearable battery-powered artificial-intelligence internet-of-things (AI-IoT) devices for continuous monitoring a wide variety of vital signs [1, 2] (Fig.
ISSCC 2013
Session 24
Digital Circuits
Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits
37V near-Vt adder array. Fig. 24.9.3(b) shows a block diagram of a test chip. 32 arrays of 32b adders are implemented with input/output latches. The critical path of each adder is 110 FO4 inverter delays. In IRC, static
ISSCC 2012
Session 25
Memory
Over-10×-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme
This paper presents solid-state drives (SSDs) with two high reliability techniques. First, an error-prediction (EP) low-density-parity-check (LDPC) errorcorrecting code (ECC) that realizes an over 10× extended lifetime.
ISSCC 2012
Session 13
Memory
A 6T SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Fails That Achieves 57% Faster Read and 31% Lower Read Energy
Semiconductor Technology Academic Research Center, Yokohama, Japan 1 2 Decreasing operating margins due to random variations is a key issue for voltage scaling in SRAM technology. It is particularly severe for half-selec
ISSCC 2010
Session 22
Image Sensors
A 256×256 14k Range Maps/s 3-D Range-Finding Image Sensor Using Row-Parallel Embedded Binary Search Tree and Address Encoder
These days, 3-D information technology is being developed rapidly and has been applied to various fields. Moreover, ultra-fast 3-D range-finding makes way for the possibilities of additional applications such as drop tes