ISSCC 2018
Session 7
Clocking & PLLs
A Secure Camouflaged Logic Family Using PostManufacturing Programming with a 3.6GHz Adder Prototype in 65nm CMOS at 1V Nominal VDD Fig. 7.6.3 shows the Shmoo plots for the pre-programmed adder design under no stress (baseline), 60 seconds reverse function stress from baseline, and 60 seconds boost stress from baseline. The 60 second reverse function stress fully alters the logic function of the pre-programmed gates. The stress voltage is 3V, resulting in a current density and voltage drop per leg of 18.4mA/μm2 and 2.67V.
With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production
ISSCC 2018
Session 4
mm-Wave
A Reconfigurable 28/37GHz Hybrid-Beamforming MIMO Receiver with Inter-Band Carrier Aggregation and RF-Domain LMS Weight Adaptation
This paper presents a hybrid beamforming mm-wave MIMO receiver with two key innovations. First, it can be configured into three modes: two single-band multistream modes at 28 or 37 GHz that can support single- or multi-u
ISSCC 2017
Session 19
Clocking & PLLs
A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter
Digital-PLL frequency synthesizers for wireless applications have become popular in the sub-10GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the integer-N type [1]. This is due to li
ISSCC 2014
Session 22
Data Converters
A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI
Low-power time-interleaved ADCs with high sampling rates of over 10GS/s are in high demand for wireline communication systems. However, the timeinterleaved channels suffer from process mismatch, particularly for timing s
ISSCC 2013
Session 8
mm-Wave
A 0.7W Fully Integrated 42GHz Power Amplifier with 10% PAE in 0.13µm SiGe BiCMOS
North Carolina State University, Raleigh, NC 1 2 In this paper, we report a fully integrated power amplifier (PA) architecture that combines the power of 16 on-chip PAs using a 16-way zero-degree combiner to achieve an o
ISSCC 2010
Session 27
RF & Wireless
An 8.6GHz 42ps Pulse-Width Electrical Mode-Locked Oscillator
This paper reports on a fully integrated electrical mode-locked oscillator. Modelocked oscillators are traveling wave oscillators that excite multiple spectral modes of a transmission line resonator and lock them in phas