ISSCC 2013
Session 20
Clocking & PLLs
A 2.4psrms-jitter Digital PLL with Multi-Output BangBang Phase Detector and Phase-Interpolator-Based Fractional-N Divider
time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2-4]. Architectures based on bang-bang phase detectors are very attractive
ISSCC 2013
Session 14
Digital Circuits
An All-Digital PLL Using Random Modulation for SSC Generation in 65nm CMOS
This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and
ISSCC 2012
Session 16
Power Management
An Optimized Driver for SiC JFET-Based Switches Delivering More Than 99% Efficiency
Nowadays, there is a high demand for highly efficient power converters that can be put in systems such as power factor correctors or solar panels. A silicon carbide (SiC) based power switch has a very good performance wh
ISSCC 2010
Session 26
Digital Circuits
A 1.4psrms-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS
State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1-3], of
ISSCC 2008
Session 9
mm-Wave
A 2kV ESD-Protected 18GHz LNA with 4dB NF in 0.13µm CMOS
10GHz is becoming extremely crowded alternative higher frequency bands are getting a large attention despite their associated high dispersion losses and need for a direct line-of-sight. Recently, numerous published work