ISSCC 2026
Session 31
Other
LUT-SSM: A 99.3TFLOPS/W LUT-Based State-Space Model Accelerator Using Energy-Efficient Element-Wise Layer Fusion and LUT-Friendly Weight-Only Quantization
Ulsan National Institute of Science and Technology, Ulsan, Korea, 4Naver Cloud, Seongnam, Korea *Equally Credited Authors (ECAs) 1 3 Abstract State-space models (SSMs) and weight-only quantization alleviate huge external
ISSCC 2026
Session 2
AI / ML
UniC-Vision: A 14.4Gb/s 7.3pJ/b Universal Vision Transformer OFDM Channel Estimation Accelerator for B5G/6G AI-RAN
Abstract This work presents an AI-RAN channel estimation accelerator for next-generation communications, offering hyper reliability, low latency, and universal frequency range coverage, thereby meeting B5G/6G requirement
ISSCC 2024
Session 3
Analog Circuits
A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C
Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea 1 2 Improving the temperature stability of the reference current (IREF) is essential for the reliable operation of precision electronics for various appli
ISSCC 2024
Session 28
Power Management
A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm2 Current-Density FoM
pervasive trend across multiple markets, including the sector for buck DC-DC converters. One of the cardinal challenges in achieving optimized power density is navigating the intrinsic trade-off between an inductor’s vol
ISSCC 2024
Session 20
AI / ML
C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models
20.5.1, are widely used, and even on-device LLM systems with real-time responses are anticipated
ISSCC 2024
Session 14
Digital Circuits
A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS
architecture is emerging as a solution for on-chip power delivery [1-6]. Multiple digital LDO (D-LDO) units cooperate inside this framework to regulate supply voltage via a shared power grid network. By evenly dispersing
ISSCC 2024
Session 10
Clocking & PLLs
A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
most popular architecture for generating ultralow-jitter signals due to their high-gain sampling phase detectors (SPDs) that can significantly reduce in-band phase noise (PN). However, to maintain this advantage even in t
ISSCC 2023
Session 4
Clocking & PLLs
A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth
The W and D bands located at the lower boundary of the sub-THz spectrum are considered viable candidates for CMOS-based wireless-communication systems to utilize sub-THz frequencies. However, there are still many challen
ISSCC 2023
Session 4
Clocking & PLLs
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
bands are still the primary spectrum for 5G communications due to their natural advantages, such as higher compatibility/interoperability with existing networks and better properties for radio transmission. To fully util
ISSCC 2023
Session 22
AI / ML
C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-NeuralNetwork Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation
have been shown to achieve the same accuracy as Convolutional-Neural-Networks (CNNs). By using CNN-to-SNN conversion, SNNs become a promising candidate for ultra-low power AI applications [1]. For example, compared to BN
ISSCC 2023
Session 2
Digital Processors
MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices
A neural radiance field (NeRF) [1] uses a deep neural network (DNN) to create 3D models by training the DNN to memorize 3D scene geometry from a few photos. Prior work uses conventional computer graphic algorithms, such