机构

Korea Advanced Institute of Science and Technology

11 篇

ISSCC 2026Session 31Other28nm FD-SOI
LUT-SSM: A 99.3TFLOPS/W LUT-Based State-Space Model Accelerator Using Energy-Efficient Element-Wise Layer Fusion and LUT-Friendly Weight-Only Quantization
Sunwoo Yoo*1,2, Dongyun Kam*3, Gunho Park4, Soonhyun Kwon1, Dongsoo Lee4, Youngjoo Lee1
提出一种基于查找表（LUT）的状态空间模型（SSM）加速器LUT-SSM，通过多对多LUT-ACC和逐元素层融合技术高效支持INT-FP的通用矩阵乘法和顺序逐元素运算，解决SSM部署中的存储访问和能效问题。在28nm FD-SOI工艺上实现99.3TFLOPS/W峰值能效。
▸提出基于LUT的many-to-many累加器（LUT-ACC），高效支持SSM中的INT-FP矩阵乘法。
▸引入逐元素（EW）层融合技术，减少外部存储访问并提升能效。
Korea Advanced Institute of Science and Technology, Daejeon,
ISSCC 2026Session 2AI / ML28nm CMOS
UniC-Vision: A 14.4Gb/s 7.3pJ/b Universal Vision Transformer OFDM Channel Estimation Accelerator for B5G/6G AI-RAN
Sangbu Yun1,2, Chanhee Lee1,2, Soonhyun Kwon1, Jeongtaek Chang3, Zhengya Zhang3, Youngjoo Lee1
该论文提出了一款用于B5G/6G AI-RAN的通用视觉变压器OFDM信道估计加速器UniC-Vision，通过算法-硬件协同优化和架构优化，在28nm CMOS工艺下实现了14.4Gb/s的吞吐量和7.3pJ/b的能效，比现有系统在可靠性上提升7.7至18.9dB，吞吐量提升16至39倍，满足超可靠低延迟的6G需求。
▸首次将视觉变压器（Vision Transformer）应用于OFDM信道估计，利用其全局注意力机制提升估计精度和鲁棒性。
▸采用算法-硬件协同优化方法，针对信道估计任务定制神经网络结构，并设计专用加速器架构，实现高吞吐量和低能耗。
Korea Advanced Institute of Science and Technology, Daejeon, 14.4Gb/s 7.3pJ/b
ISSCC 2024Session 3Analog Circuits
A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C
Pangi Park1, Junghyup Lee2, SeongHwan Cho1
该论文提出了一种PVT不敏感的亚分档电流基准电路，通过亚分档技术实现了在-20°C到125°C宽温度范围内仅11.4ppm/°C的极低温度系数，解决了传统电流基准温度稳定性不足的问题。
▸提出亚分档电流基准架构，结合PTAT和CTAT电流加权，实现PVT不敏感
▸在宽温度范围内达到11.4ppm/°C的超低温度系数，适用于汽车和工业传感器等精密电子设备
Korea Advanced Institute of Science and Technology, Daejeon, 11.4ppm/°C温度系数，-20°C到125°C
ISSCC 2024Session 28Power Management
A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm2 Current-Density FoM
Hyunki Han, Jeong-Hyun Cho, Woojin Jang, Yousung Park, Jiho Lee, Hyun-Sik Kim
该论文提出了一种并联开关电容混合降压转换器，通过电压转换比感知拓扑优化器来优化拓扑结构，旨在解决紧凑电感下DCR升高导致的效率下降问题。实现了94.1%的峰值效率和4.2A/mm²的电流密度。
▸提出了一种电压转换比感知的拓扑优化器，能够自动搜索最优的并联开关电容混合降压拓扑。
▸通过并联开关电容路径分担部分功率传输，显著降低了电感电流，从而允许使用更小体积的电感并提升功率密度。
Korea Advanced Institute of Science and Technology, Daejeon, 94.1% peak efficiency, 4.2A/mm² current density
ISSCC 2024Session 20AI / ML
C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models
Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Hoi-Jun Yoo
该论文提出了一种名为C-Transformer的同质DNN-Transformer/Spiking-Transformer处理器，通过大-小网络架构实现了2.6-18.1μJ/Token的高能效处理，解决了传统Transformer模型在边缘设备上计算和能耗过高的问题。
▸提出大-小网络架构，结合DNN和Spiking神经网络，实现灵活高效的混合模型处理。
▸采用同质处理器设计，支持DNN-Transformer和Spiking-Transformer两种模式的无缝切换。
Korea Advanced Institute of Science and Technology, Daejeon, 2.6-18.1μJ/Token
ISSCC 2024Session 14Digital Circuits
A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS
Yong-Jin Lee1,2, Woojin Jang1,2, Hong-Hyun Bae1, Jeong-Hyun Cho1, Hyun-Sik Kim1
architecture is emerging as a solution for on-chip power delivery [1-6]. Multiple digital LDO (D-LDO) units cooperate inside this framework to regulate supply voltage via a shared power grid network.
Korea Advanced Institute of Science and Technology, Daejeon,
ISSCC 2024Session 10Clocking & PLLs
A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
Yuhwan Shin*1,2, Junseok Lee*1,2, Juyeop Kim*1,2, Yongwoo Jo1,2, Jaehyouk Choi2
本文提出了一种采用非线性复制技术的分数-N采样锁相环（SPLL），有效抑制了数字时间转换器（DTC）非线性引起的分数杂散和带内相位噪声恶化，实现了76fsrms的极低抖动和-65dBc的分数杂散性能。该技术通过复制DTC的非线性特性并加以补偿，解决了传统DTC方案中非线性限制SPLL在分数-N模式下性能的关键问题。
▸提出非线性复制技术（Nonlinearity-Replication Technique），通过复制并补偿DTC的非线性，显著降低分数杂散和带内相位噪声。
Korea Advanced Institute of Science and Technology, Daejeon, 76fsrms jitter, -65dBc fractional spur
ISSCC 2023Session 4Clocking & PLLs
A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth
Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi
The W and D bands located at the lower boundary of the sub-THz spectrum are considered viable candidates for CMOS-based wireless-communication systems to utilize sub-THz frequencies. However, there ar
Korea Advanced Institute of Science and Technology, Daejeon,
ISSCC 2023Session 4Clocking & PLLs
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
Yongwoo Jo*, Juyeop Kim*, Yuhwan Shin, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
本文提出了一种基于单LC-VCO的亚采样PLL和环形振荡器子采样的LO发生器，覆盖0.6至7.7GHz频率范围，实现了135fsrms的抖动性能，解决了5G FR1全频段LO生成的高效设计挑战。
▸采用单LC-VCO亚采样PLL结合环形振荡器子采样架构，实现宽频率范围覆盖。
▸通过优化环路设计和噪声抑制技术，在宽频带内保持低抖动性能。
Korea Advanced Institute of Science and Technology, Daejeon, 135fsrms jitter @ 0.6-7.7GHz
ISSCC 2023Session 22AI / ML
C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-NeuralNetwork Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Hoi-Jun Yoo
提出一种异构CNN/SNN核心架构的深度神经网络处理器C-DNN，通过互补利用CNN和SNN的优势，实现24.5-85.8 TOPS/W的高能效。解决了SNN能量随层间尖峰稀疏性波动的问题，同时保持高准确率。
▸首次提出互补深度神经网络（C-DNN）处理器，在同一芯片上集成CNN和SNN异构核心，根据层间尖峰稀疏性动态选择计算模式。
▸通过事件驱动与帧驱动混合计算，优化能量效率，实现24.5-85.8 TOPS/W的峰值能效。
Korea Advanced Institute of Science and Technology, Daejeon, 24.5-85.8 TOPS/W
ISSCC 2023Session 2Digital Processorsnull
MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices
Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
本文提出MetaVRain，一种用于移动端元宇宙的实时超逼真3D NeRF处理器，功耗仅133mW。通过设计1D-2D混合神经网络引擎，实现了高效低功耗的NeRF推理，解决了NeRF在移动设备上实时运行的难题。
▸提出1D-2D混合神经网络引擎，结合1D和2D计算优势，降低计算复杂度
▸实现133mW超低功耗下的实时3D NeRF渲染，适用于移动元宇宙场景
Korea Advanced Institute of Science and Technology, Daejeon, 133mW功耗，实时渲染（具体帧率未给出）