ISSCC 2022
Session 17
Wireline I/O
A 10Gb/s Digital Isolator Using Coupled Split-Ring Resonators with 24kVpk Surge Capability and 100kV/µS Common-Mode Transient Immunity
High speed data links play a key role in industrial and medical systems. Galvanic isolation in high-speed links ensures the safety of human operators and instruments. Optoisolators generally achieve high voltage ratings
ISSCC 2019
Session 8
Power Management
A 2MHz 4-to-60VIN Buck-Boost Converter for Automotive Use Achieving 95% Efficiency and CISPR 25 Class 5 Standard
High-voltage highly efficient switching power converters have gained high popularity in automotive applications. Powered by the car battery (VIN), the converters need to experience a wide VIN range from 4V to 60V under ha
ISSCC 2019
Session 10
RF & Wireless
An Energy Measurement Front-End with Integrated In-Situ Background Full System Accuracy Monitoring Including the Current and Voltage Sensors
to determine billable energy consumption. These devices are factory calibrated, and then perform measurement without interruption over their lifetime. Once in the field their accuracy is unknown due to component aging and
ISSCC 2018
Session 1
Plenary
Semiconductor Innovation: Is the party over, or just getting started?
Semiconductor Innovation Trends: The hardware paradigm underpinning the Information and Communications Technology (ICT) industry has experienced three major shifts over the past 60 years - the mainframe era, the personal
ISSCC 2017
Session 5
Analog Circuits
A 19nV/√Hz-Noise 2μV-Offset 75μA Low-Drift Capacitive-Gain Amplifier with Switched-Capacitor ADC Driving Capability
(CGA) with amplifier common-mode sampling (CMS) and switched-capacitor driving capability, compatible with many conventional switched-capacitor ADC inputs (SCAI) such as delta-sigma modulators or SAR ADCs. CGAs are popul
ISSCC 2017
Session 16
Data Converters
A 9GS/s 1GHz-BW Oversampled Continuous-Time Pipeline ADC Achieving -161dBFS/Hz NSD
front-end by a switchedcapacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving curr
ISSCC 2016
Session 21
Wireless
A 200nA Single-Inductor Dual-Input-Triple-Output (DITO) Converter with Two-Stage Charging and Process-Limit Cold-Start Voltage for Photovoltaic and Thermoelectric Energy Harvesting
Analog Devices, Wilmington, MA, 3 Analog Devices, San Jose, CA 1 2 Energy harvesting has been considered to be a good solution to power many IoE applications [1-3]. Some applications require regulated supply voltage, whi
ISSCC 2015
Session 25
RF & Wireless
A Highly-Digital Frequency Synthesizer Using RingOscillator Frequency-to-Digital Conversion and Noise Cancellation
Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and lo
ISSCC 2013
Session 26
Data Converters
A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS
veryhigh-SNR applications where the precision and stability of capacitors are leveraged along with the use of large signal swings [1], and (b) in high-speed, lowresolution applications [2, 3] in which the SAR’s low power
ISSCC 2012
Session 27
Data Converters
A 14b 3/6GHz Current-Steering RF DAC in 0.18µm CMOS with 66dB ACLR at 2.9GHz
The growth in communications coupled with the move towards multi-carrier, multi-band, multi-standard radio transmitters have helped drive high-speed digital-to-analog converter (DAC) technology for over a decade. The cri
ISSCC 2012
Session 21
Analog Circuits
A 60V Capacitive Gain 27nV/√Hz 137dB CMRR PGA with ±10V Inputs
Analog Devices, Valencia, Spain 1 2 This paper describes the implementation of a 60V programmable-gain amplifier (PGA) with ±10V differential input range and a 5V output compatible with many commercially available ADCs.
ISSCC 2009
Session 24
Wireless
A 2.4GHz 2Mb/s Versatile PLL-Based Transmitter Using Digital Pre-Emphasis and Auto Calibration in 0.18µm CMOS for WPAN
A fully integrated 2.4GHz 2Mb/s transmitter which is part of a highly integrated WPAN RF transceiver SoC using a 0.18µm RFCMOS 1P6M process is presented. The transmitter uses a ∆Σ fractional-N PLL architecture. It transm
ISSCC 2009
Session 2
Image Sensors
A 4-Channel 20-to300 Mpixel/s Analog Front-End with Sampled Thermal Noise Below kT/C for Digital SLR Cameras ply nodes VDD and VSS caused by parasitic inductance, limiting crosstalk. Also, the floating current mirror formed by MN1 and MN2 allows the bias current to be easily optimized by the nonlinear bias generator described earlier.
Analog Devices, Beijing, China With this new reference buffer, measured crosstalk exceeds -85dB. A fullscale step input is applied to the aggressor channel, and other channels are measured with inputs grounded. Channel m