ISSCC 2024
Session 33
AI / ML
A Multi-Loop Neuromodulation Chipset Network with Frequency-Interleaving Front-End and Explainable AI for Memory Studies in Freely Behaving Monkeys
of dementia, affects over 30 million people worldwide and accounts for more than 1% of the global GDP [1]. Given that age is a significant risk factor, the number of AD patients is projected to double in the next two deca
ISSCC 2018
Session 6
Wireline I/O
A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshold ADC in 16nm FinFET
for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantiza
ISSCC 2017
Session 6
Wireline I/O
A 28Gb/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance
(CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes th
ISSCC 2016
Session 23
Wireline I/O
A 16Gb/s 1 IIR + 1 DT DFE Compensating 28dB Loss with Edge-Based Adaptation Converging in 5μs
I/O receivers routinely equalize ISI over 10 or more post-cursor UI. IIR DFEs are a low-power technique for canceling long post-cursor ISI tails, and have been demonstrated compensating over 20dB loss at fbit/2 up to 10G
ISSCC 2016
Session 20
RF & Wireless
A 1.92mW Filtering Transimpedance Amplifier for RF Current Passive Mixers
Nowadays, current passive mixers represent the state of the art for signal downconversion in wireless receivers. In such kind of structures, noise, distortions and losses are strictly correlated to the performance of the
ISSCC 2015
Session 13
RF & Wireless
A 600μW Bluetooth Low-Energy Front-End Receiver in 0.13μm CMOS Technology
*Now at Qualcomm, San Diego, CA One of the main goals for the next generation of radios for wireless sensor and body-area networks (WSN and WBAN) is a sub-mW receiver (RX) compliant with energy-harvested supplies. In thi
ISSCC 2012
Session 4
RF & Wireless
A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp Differential Swing
for higher integration of wireless transceivers in deeply-scaled silicon technologies. Given the overwhelming digital content of a mobile platform, ideally, the RF components should be realized with topologies that allow
ISSCC 2010
Session 8
Wireline I/O
A 6.8mW 7.4Gb/s Clock-Forwarded Receiver with up to 300MHz Jitter Tracking in 65nm CMOS
High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 - 20 data transceivers. Sub-rate clocks ameliorate j
ISSCC 2009
Session 9
Data Converters
A 50MS/s 9.9mW Pipelined ADC with 58dB SNDR in 0.18µm CMOS Using Capacitive Charge-Pumps
pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined
ISSCC 2009
Session 14
Digital Circuits
A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO Detector
The high spectral efficiency offered by multiple-input-multiple-output (MIMO) technology has made it the technology-of-choice in many standards like IEEE 802.16e/m (WiMAX) and the long term evolution (LTE) project and em
ISSCC 2008
Session 18
Other
A 0.18µm CMOS Integrated Sensor for the Rapid Identification of Bacteria
There is widespread demand for a low-cost, rapid, selective and sensitive method for detecting bacteria in medical diagnosis, and food-safety inspection. Traditional methods, such as polymerase chain reaction and cell cu