ISSCC 2026
Session 8
Wireline I/O
A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS
*Equally Credited Authors (ECAs) 1 Abstract This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decoup
ISSCC 2026
Session 32
Data Converters
An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization
Abstract This paper presents an incremental pipeline ADC with dual-residue architecture. An exponential ΔΣ loop is proposed to directly quantize the residue, replacing conventional interpolators that are complex and less
ISSCC 2026
Session 31
Other
VARSA: A Visual Autoregressive Generation Accelerator Using Performance-Scalable Multi-Precision PE-LUT and Grid-Similarity Attention Compression
Abstract This paper presents VARSA, a 22nm visual autoregressive accelerator for efficient text-toimage generation, featuring: 1) a performance-scalable hybrid PE-LUT core; 2) multi-precision parallel processing with run
ISSCC 2026
Session 18
AI / ML
A 22nm 1.87ms/Frame Streaming Multi-Speaker ASR Accelerator Leveraging Contextual-Aware Redundancy Skipping with 2D-Writable Microscaling Compute-in-Memory and Similarity-Aware TCAM Design
*Equally Credited Authors (ECAs) Abstract This paper presents a DCIM-based accelerator for on-device streaming multi-speaker ASR (MS-ASR), featuring: 1) a context-aware redundancy skipping scheme with online sparse block
ISSCC 2026
Session 11
Data Converters
A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration
Abstract This paper presents a 14b 400MS/s Pipelined-SAR ADC utilizing a front-end TDC with a linearized rail-to-rail input VTC. A background calibration engine corrects VTC gain and timedomain offset errors by monitorin
ISSCC 2026
Session 10
Digital Circuits
A 28nm Mode-Reconfigurable CAM-CIM Hybrid Complete 3-SAT Solver Supporting Conflict-Driven Clause Learning with 100% Solvability
Abstract The K-SAT problem is NP-complete and costly on von Neumann machines. Several ASIC solvers have been proposed to mitigate this, but they rely on inefficient crossbar mapping, overlook community structures and lac
ISSCC 2025
Session 37
AI / ML
A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation
Initially applied for image synthesis [1], Diffusion Models (DMs) have been rapidly expanded into many content-generation tasks, e.g. 3D scenes [2-3] or video [4], and deliver exceptional performance. Figure 37.6.1 provi
ISSCC 2025
Session 18
Data Converters
A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting
With the development of high-resolution ADCs (>13b) leveraging the SAR topology, the pursuit of power efficiency in ADC design continues to make remarkable strides [1-5]. However, as the capacitance of the capacitive DAC
ISSCC 2025
Session 18
Data Converters
A 184.8dB-FoMS 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique
high-resolution ∆Σ modulator, is favored for sensor nodes demanding high accuracy, good energy efficiency, and easy system integration. Conventional zoom ADCs, constrained by the low quantization levels of ∆Σ modulators,
ISSCC 2023
Session 6
Wireline I/O
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS
The ever-growing demands for high-bandwidth communications continuously push wireline links to operate at higher speeds. Recently reported transmitters (TXs) have achieved a data rate of more than 100Gb/s [1-6]. PAM-4 mo
ISSCC 2023
Session 6
Wireline I/O
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS
The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time fe
ISSCC 2023
Session 10
Data Converters
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer
good energy efficiency. Lately, the incremental ADC is drawing rising attention by favoring system integration with its easy multiplexing and simple digital filtering. By combining a low-power SAR with a low-distortion ∆
ISSCC 2022
Session 17
Wireline I/O
A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS
cloud computing, have significantly driven the requirement for high transmission data rates. Polarization diversity coherent detection is an indispensable technique for realizing high-capacity transmission owing to its e
ISSCC 2018
Session 6
Wireline I/O
A 32Gb/s 133mW PAM-4 Transceiver with DFE Based on Adaptive Clock Phase and Threshold Voltage in 65nm CMOS
With the proliferation of the Internet of Things and mobile computing, network speed is accelerating to support data-rich services. This drives the explosion of bandwidth requirement on backplane interconnects while chan