Toshiba

Abstract A binary-weighted switched-capacitor gate driver IC achieving up to 85% reduction in driving loss (Edrv) is presented. Four binary-weighted flying capacitors enable nine-level gate-voltage segmentation, enhancin

Abstract A digital feedback active gate driver IC applicable to both high- and low-side 600A, 1200V SiC MOSFETs is proposed and demonstrated on the high-side. High-side voltage sensing uses a parasitic Miller capacitance

Increased switching frequency of power devices for power electronics allows for compact and lightweight circuit implementations for variety of applications, including power factor corrections, DC/DC converters, and motor

Active gate control is an emerging technique to minimize the switching loss of highpower converters facing noise-suppression challenges. In a conventional gate-driver design, a fixed value of gate resistance is chosen by

Switched-capacitor (SC) DC-DC converters have gained attention based on their ability to offer a low-cost high-efficiency power conversion, and allow a thin and compact module packaging [1]. However, the SC DC-DC convert

Low-cost CMOS PAs for mobile terminals have been a focus of attention in recent years. Self-contained, linear CMOS PAs are particularly attractive for smooth replacement of conventional compound semiconductor PA products

control gain, KVCO, increases the phase noise contribution arising from the charge pump and loop filter. To resolve this problem, dual-tuning PLLs (DT-PLLs) have been studied [1-4]. The DT-PLL structure adds a narrow-ban

Sampling clock jitter significantly degrades the circuit performance and dynamic range of an ADC [1]. This paper presents a 570fsrms integrated-jitter 1.21GHz PLL with a hybrid loop. A ring VCO has a much inferior phase

Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques

is one of the promising candidates for realizing a CMOS radar IC [1-3]. Range and velocity resolutions of the FMCW radar are determined by the bandwidth and period of triangular modulation [4]. A short-range measurement

implemented for monolithic integrated System on Chip (SoC) by applying the advantages of process compatibility between MEMS and CMOS LSI [1]. However, it has been impossible to integrate them in the case that MEMS and st

Recently, signals with high peak-to-average power ratio (PAPR) are being used for metropolitan area networks (MANs) and cellular systems, and therefore highly linear transmitters (Txs) are required. The linearity perform

In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and

In this paper, a scheme for tuning cutoff-frequency of filters is presented. Instead of using a multibit resistor bank, a 1b switched-resistor structure operating at 200MHz is utilized. The effective RC time constant is

A mixer is one of the bottlenecks in achieving the low-voltage operation of a receiver. Most of the mixer topologies recently reported for low-voltage and low-power applications can be categorized into bulk-injection mix