ISSCC 2026
Session 7
Image Sensors
A 128×96 Multimodal Flash LiDAR SPAD Imager with Object Segmentation Latency of 18μs Based on Compute-Near-Sensor Ising Annealing Machine
*Equally-Credited Authors (ECAs) Abstract This paper presents a 128×96 multimodal flash LiDAR SPAD imager integrated with a compute-near-sensor Ising-model annealing processor for dynamic object segmentation, framed as a
ISSCC 2026
Session 37
Memory
A 16Gb/s/pin 0.51pJ/b Single-Ended NRZ Transceiver with Distributed Dual-Loop VDDQ-Ripple Compensation and Dynamic Clock Duty-Cycle Calibration for Memory Interfaces
*Equally Credited Authors (ECAs) 1 Abstract A 16Gb/s/pin 0.51pJ/b single-ended NRZ transceiver with distributed dual-loop compensation (DDLC) for VDDQ-ripple suppression and dynamic duty-cycle calibration (DDCC) for robu
ISSCC 2026
Session 33
RF & Wireless
A 6GHz Quadrature Digital Transmitter Supporting a 1GHz Signal Bandwidth with <-40dB EVM Floor and >55dB Dynamic Range in 28nm CMOS
*Equally Credited Authors (ECAs) Abstract A 6GHz quadrature DTX supporting a 1GHz signal bandwidth is presented in 28nm CMOS, where static and dynamic nonlinearities are carefully optimized. Occupying a core area of 0.67
ISSCC 2026
Session 25
Hardware Security
A 28nm 0.48mJ/boot Torus FHE Processor for Arbitrary Computation on Encrypted Data
Abstract This work presents a 3.24mm2 torus fully homomorphic encryption (FHE) processor fabricated in 28nm CMOS, featuring: 1) a security-preserving low-bit-width torus quantization with keys hints reducing latency by 6
ISSCC 2026
Session 21
RF & Wireless
A Temperature- and Aging-Compensated TMR Current Sensor with ±0.13% Sensitivity Variation from -40°C to 120°C
Abstract This paper presents a TMR-based contactless current sensor that mitigates sensitivity drift due to temperature and aging. The proposed sensitivity stabilization loop continuously adjusts the TMR sensitivity, mak
ISSCC 2026
Session 14
Other
THz-TSI: A 0.33pJ/b 264Gb/s Through-Silicon Interconnect Module for 3D Integration Utilizing Terahertz Coupling
Abstract A through-silicon interconnect module for 3D integration utilizing THz coupling is presented, which achieves a record high data rate of 264Gb/s and efficiency of 0.33pJ/b. Both bidirectional point-to-point link
ISSCC 2026
Session 12
AI / ML
A 10.2-to-16.2GHz Dual-Mode-Transformer-Based Wideband Series-Resonance VCO Achieving >201.1dBc/Hz FoMT at a 10MHz Offset
Abstract This work presents a 28nm CMOS SR-VCO enabled by a dual-mode transformer with magnetic control, achieving a wide tuning range of 10.2 to 16.2GHz (45.2%) and a high FoMT/FoMAT@10MHz of 201.1/207.7dBc/Hz. A transf
ISSCC 2025
Session 7
Wireline I/O
An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS
Multi-phase clock generation is among the most critical building blocks in high-speed wireline transceivers. The integrated jitter and phase error of the clocks often dictate the maximum available SNDR at higher frequenc
ISSCC 2025
Session 26
Wireless
A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOS
*Equally Credited Authors (ECAs) There are multiple wireless communication standards in the crowded sub-6GHz band and the trend of data throughputs is continuously increasing. In the last few years, digital transmitters
ISSCC 2025
Session 11
Wireless
A 200MHz-BW Blocker-Tolerant Receiver with Fifth-Order Filtering Achieving 19dBm Adjacent-Channel IIP3
The fifth-generation (5G) New-Radio (NR) standard has been developed for high data-rate communication, with the RF channel bandwidth (BW) extending to several hundred megahertz. In this context, the presence of blockers
ISSCC 2024
Session 4
RF & Wireless
A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection
technologies, it is desirable to completely digitize the transmitter, which yields reduced die area, highly efficient operation and direct interface to digital baseband. However, the ever-increasing data demand with compl
ISSCC 2023
Session 31
RF & Wireless
A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40% System Efficiency for Multi-Mode NB-IoT/BLE Applications
Cellular narrowband Internet-of-Things (NB-IoT) is an important branch of low-power wide-area IoT applications, which specifies multiple operation bands over 663 to 915MHz (LB) and 1710 to 2010MHz (MB), up to 23dBm outpu
ISSCC 2022
Session 20
RF & Wireless
A 0.5mΩ/√Hz 106dB SNR 0.45cm2 Dry-Electrode Bioimpedance Interface with Current Mismatch Cancellation and Boosted Input Impedance of 100MΩ at 50kHz
Bioimpedance (BioZ) analysis has been recognized as a new paradigm to derive a number of body composition and hemodynamic measures in a non-invasive manner. Measuring the changes in electrical resistance of the thorax du
ISSCC 2022
Session 13
Digital Circuits
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency
University of Washington, Seattle, WA 1 2 The digital injection-locked clock multiplier (ILCM) using ring oscillators (ROs) is a superior choice for clock generation due to its ease of scaling, compact area, and prominen
ISSCC 2020
Session 24
AI / ML
A 15b Quadrature Digital Power Amplifier with Transformer-Based Complex-Domain Power-Efficiency Enhancement
law to provide compact die area, better interface to digital back-end, and higher power efficiency due to the faster switching nature of core devices even in face of reduced supply voltages. Moreover, the integration of
ISSCC 2019
Session 4
AI / ML
A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement
Sophisticated OFDM modulation schemes with high spectrum efficiency and data throughput in modern wireless communication systems often result in a large peak-to-average power ratio (PAPR). Besides, wireless standards like
ISSCC 2019
Session 26
RF & Wireless
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity
Intensive interest in internet-of-things devices has crowded the ISM bands (e.g., 2.4GHz). A robust receiver for each wireless link in such a coexistence environment is required not only to have high rejection of out-of-
ISSCC 2018
Session 26
AI / ML
A Compact Dual-Band Digital Doherty Power Amplifier Using Parallel-Combining Transformer for Cellular NB-IoT Applications
Narrowband Internet-of-Things (NB-IoT) is a newly developed 3GPP protocol optimized for low-power wide-area IoT applications and is evolving toward the future fifth-generation (5G) mobile communication. It specifies at l
ISSCC 2014
Session 4
Power Management
An 87%-Peak-Efficiency DVS-Capable SingleInductor 4-Output DC-DC Buck Converter with Ripple-Based Adaptive Off-Time Control
Improving battery longevity in portable devices usually requires the use of different voltage levels with a wide range of load capability for various functional blocks. Since a single-inductor-multiple-output (SIMO) conv
ISSCC 2013
Session 20
Clocking & PLLs
A 50-to-930MHz Quadrature-Output Fractional-N Frequency Synthesizer with 770-to-1860MHz SingleInductor LC-VCO and Without Noise Folding Effect for Multistandard DTV Tuners
Ratio Microelectronics, Shanghai, China 1 2 There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. I
ISSCC 2009
Session 23
Clocking & PLLs
A 975-to-1960MHz Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners
Ratio Microelectronics, Shanghai, China 1 2 There is a high demand for high-performance tuners to meet the digital video broadcasting-terrestrial (DVB-T) standard. Often the DVB-T tuners employ a double-conversion zero-I