ISSCC 2026
Session 11
Data Converters
A 28nm CMOS SAR-Based Continuous-Time Pipeline ADC with 103dB SFDR and 270MHz Bandwidth Using NCF and DAC Error Calibration
receivers achieves -95dBc THD and 103dB SFDR in 270MHz bandwidth, exceeding state-of-the-art by >20dB. Wideband high spectral purity is realized with a highly linear all-pass filter, high- SFDR coarse ADCs, a fast tone-b
ISSCC 2024
Session 32
Power Management
A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer
require virtual MIMO antenna arrays with hundreds of elements. To operate such arrays without compromising range and velocity resolution and to have a sufficient SNR for a longrange operation, FMCW MIMO radars require fas
ISSCC 2020
Session 9
Data Converters
A Low-Cost 4-Channel Reconfigurable Audio Interface for Car Entertainment Systems
multistandard radio, parallel-channel radio reception [1], noise cancellation, HD audio and more audio interfacing possibilities. This asks for more signal processing, and therefore, a move to more expensive deep-submicr
ISSCC 2014
Session 4
Power Management
3-Phase 6/1 Switched-Capacitor DC-DC Boost Converter Providing 16V at 7mA and 70.3% Efficiency in 1.1mm3
In this paper, a 3-phase switched-capacitor (SC) boost converter that uses 2 external floating capacitors to provide 16V output from a 3.3V input is presented. It achieves an efficiency of 70.3% at 7mA load current while
ISSCC 2014
Session 17
Analog Circuits
A 0.07mm2 2-Channel Instrumentation Amplifier with 0.1% Gain Matching in 0.16μm CMOS
are required for cost-constrained automotive applications. Instrumentation amplifiers (IA) for such front-ends must process multi-channel sensor outputs and provide gain matching over the channels for proper sensor opera
ISSCC 2011
Session 3
RF & Wireless
A 5.3GHz Digital-to-Time-Converter-Based Fractional-N All-Digital PLL
Advanced deep-submicron CMOS processes are well-suited for a digital implementation of phase-locked loop-(PLL) based frequency synthesizers. Recently, several RF all-digital phase-locked loops (ADPLL) have been reported
ISSCC 2011
Session 21
RF & Wireless
A Compact SAW-less Multiband WCDMA/GPS Receiver Front-End with Translational Loop for Input Matching
In FDD systems such as WCDMA, strong TX leakage presented at RX imposes stringent RX out-of-band (OOB) IIP3 and IIP2 requirements in addition to low noise figure (NF) requirement, usually necessitating an inter-stage SAW
ISSCC 2011
Session 10
Data Converters
A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5dB SNDR up to Nyquist
many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die [1] could be simplified with a low-power 10b ADC that can digitize the e
ISSCC 2010
Session 4
Analog Circuits
A Single-Trim CMOS Bandgap Reference with a 3σ Inaccuracy of ±0.15% from -40°C to 125°C
15% (3σ) from -40ºC to 125ºC. This level of performance, previously only achieved by trimming at two or more temperatures [1, 2], was obtained by using chopping and curvature correction to minimize non-PTAT (proportional
ISSCC 2010
Session 3
RF & Wireless
A 45nm WCDMA Transmitter Using Direct Quadrature Voltage Modulator with High Oversampling Digital Front-End
In FDD systems such as WCDMA and LTE, simultaneous TX and RX operation poses a stringent TX noise floor requirement at the RX band. To eliminate the SAW filter between the TX and the PA without desensitizing the RX in WC
ISSCC 2009
Session 6
RF & Wireless
A 45nm Low-Power SAW-less WCDMA Transmit Modulator Using Direct Quadrature Voltage Modulation
In FDD systems such as WCDMA and LTE, TX and RX operate simultaneously, while the duplexer provides the necessary isolation between them. In order not to desensitize the RX path, the TX noise in WCDMA band 1 has to be lo
ISSCC 2008
Session 6
RF & Wireless
A 0.6-to-10GHz Receiver Front-End in 45nm CMOS
various standards including those for cellular, WLAN and WPAN applications. Software-defined radios (SDRs) are being considered as a likely platform to build tomorrow’s handsets. The receiver in such radios can be tuned
ISSCC 2008
Session 27
Data Converters
An Inverter-Based Hybrid ΣΔ Modulator
Feature-size scaling [1] of modern CMOS technologies dictated by Moore’s law enables integration of extensive digital signal processing at low power consumption and small area. As the area of digital functions scales wit