ISSCC 2026
Session 12
Clocking & PLLs
A –66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC
inverse-constant-slope DTC for rejection of supply disturbances is presented. Compared to traditional fractional-N digital PLLs, it requires no additional calibration for supply rejection or additional supply-insensitive
ISSCC 2018
Session 15
RF & Wireless
A Low-Phase-Noise Digital Bang-Bang PLL with Fast Lock Over a Wide Lock Range
power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolu
ISSCC 2016
Session 28
Medical & Bio
CMOS Monolithic Airborne-Particulate-Matter Detector Based on 32 Capacitive Sensors with a Resolution of 65zF rms
matter (PM) is well known [1]. Although optical and gravimetric instruments are available to detect PM, they lack portability, have poor potential for miniaturization, and are not low cost. Instead, a better spatio-tempo
ISSCC 2014
Session 2
Wireline I/O
A Background Calibration Technique to Control Bandwidth in Digital PLLs
parameters that are subject to process, temperature and voltage spreads, as well as to variations along the frequency-tuning range. Even in digital PLLs, which rely on a digital loop filter, the bandwidth still depends o
ISSCC 2014
Session 17
Analog Circuits
CMOS Impedance Analyzer for Nanosamples Investigation Operating up to 150MHz with Sub-aF Resolution
Impedance analyzers find an important role in nanoscience and in biological research as a tool to access electrical and physical parameters of the matter as well as to enhance the read-out performance in sensor applicati
ISSCC 2012
Session 20
RF & Wireless
A 20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power
Polar or outphasing radio transmitter architectures promise higher efficiency than their Cartesian counterparts [1], but require the adoption of phase modulators with bandwidth about one order of magnitude wider than the
ISSCC 2010
Session 2
RF & Wireless
Suppression of Flicker Noise Upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz Band
Flicker noise up-conversion into close-in 1/f3 phase noise is still one of the major issues in the design of CMOS oscillators. Suppression techniques have been recently presented suggesting (i) adoption of a resonant net
ISSCC 2009
Session 20
Sensors
An Instrument-on-Chip for Impedance Measurements on Nanobiosensors with attoFarad Resolution
Impedance measurements play a fundamental role in biotechnology, serving both as an investigation tool and as a direct detection technique. Tracking impedance over time is extensively used for spatial monitoring, imaging