ISSCC 2026
Session 27
Clocking & PLLs
A 48-to-82.5GHz CMOS Split-Tail Gilbert-Cell Frequency Doubler Achieving 11% PAE at 8.5dBm Output Power
Abstract A 48-to-82.5GHz frequency doubler in 28nm FDSOI CMOS using a modified Gilbert cell is presented. The tail transconductors are split and the switching-quad transistors AC-shorted by capacitors. DC offset builds u
ISSCC 2025
Session 33
Other
A 125-to-170GHz Power-Efficient Phase Shifter in SiGe BiCMOS with Outphasing Gain and Phase Corrections
Advancements in silicon technologies are opening the way to sub-THz phased-array transceivers, enabling high-resolution radar sensors, and wireless communications with a fiber-like transport capacity. Programmable phase
ISSCC 2022
Session 9
mm-Wave
Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM
The phase noise of oscillators limits the modulation Error Vector Magnitude (EVM) in wireless communications and the SNR in high-speed data converters. The issue is particularly critical in the wireless infrastructure fo
ISSCC 2017
Session 2
Power Management
A SiGe BiCMOS E-Band Power Amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB Back-Off Leveraging Current Clamping in a Common-Base Stage
now with HiSilicon-Technologies, Milan, Italy 2 Several spectrum portions at mm-waves are considered for Gb/s data-rates in 5G cellular wireless backhaul and access networks, further motivating innovation in circuits and
ISSCC 2016
Session 5
Analog Circuits
A 420μW 100GHz-GBW CMOS ProgrammableGain Amplifier Leveraging the Cross-Coupled Pair Regeneration
Cross-coupled pairs are certainly among the most widely adopted fundamental circuits still in use today. This elegant device arrangement yields broadband positive feedback with high gain and low power, desirable features
ISSCC 2013
Session 5
RF & Wireless
SAW-Less Analog Front-End Receivers for TDD and FDD either of the two inputs is low. The divider gives a quadrature 25% duty-cycle clock with -174dBc/Hz phase noise at 20MHz offset for 6mA of current consumption (simulated from extracted layout).
*Now at the University of Toronto, Toronto, ON, Canada 2 In cellular receivers, out-of-band blockers are generally managed by surfaceacoustic-wave (SAW) filters between the antenna and the low-noise amplifier (LNA). For
ISSCC 2013
Session 20
Clocking & PLLs
A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz Minimum Noise FOM Using Inductor Splitting for Tuning Extension
Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due
ISSCC 2012
Session 21
Analog Circuits
A 90Vpp 720MHz GBW Linear Power Amplifier for Ultrasound Imaging Transmitters in BCD6-SOI
Transducer drivers for ultrasound imaging are required to have high output power and operation frequency into the MHz range. Furthermore, in harmonic imaging, a well-established method resulting in enhanced contrast, hig
ISSCC 2012
Session 20
RF & Wireless
A 6.7-to-9.2GHz 55nm CMOS Hybrid Class-B/Class-C Cellular TX VCO
Lund University, Lund, Sweden 3 ST-Ericsson, Lund, Sweden 1 2 The design of very-wide-band CMOS voltage-controlled oscillators (VCOs) compliant with the phase-noise specifications of cellular transmitters is non-trivial,
ISSCC 2012
Session 20
RF & Wireless
A 36mW/9mW Power-Scalable DCO in 55nm CMOS for GSM/WCDMA Frequency Synthesizers
Lund University, Lund, Sweden 1 2 The RF front-ends of modern smart phones are becoming more complicated as newer standards are introduced (e.g. LTE). Reconfigurability can be used to reduce their size, provided that pow
ISSCC 2011
Session 27
Data Converters
A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140µW
This third-order ΔΣ modulator [1, 2], suitable for high-resolution low-power sensor systems, consumes 140µW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step The DACs u
ISSCC 2010
Session 4
Analog Circuits
Class-G Headphone Driver in 65nm CMOS Technology
and DMB reception. The users may wish to use these features for many hours and a low efficiency amplifier could deplete the battery in a short time. There are two classes of power amplifiers usually used for this applica
ISSCC 2010
Session 2
RF & Wireless
GHz DCO with a Frequency Resolution of 150Hz for All-Digital PLL
In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. I
ISSCC 2009
Session 19
Analog Circuits
A 1.25mW 75dB-SFDR CT Filter with In-Band Noise Reduction
In a direct-conversion wireless receiver the baseband filter should be able to handle large blockers, resulting in a very challenging spurious free dynamic range (SFDR) requirement. In particular, the noise added in-band
ISSCC 2009
Session 12
RF & Wireless
A Low-Noise Active Balun with IM2 Cancellation for Multiband Portable DVB-H Receivers
Broadband low noise amplifiers are needed in a variety of applications, from multistandard cellular receivers to terrestrial and handheld TV tuners [1,2]. For broadband and multiband operation, intermodulation and cross-
ISSCC 2008
Session 12
Data Converters
A 9.4-ENOB 1V 3.8µW 100kS/s SAR ADC with TimeDomain Comparator
The signal bandwidth used in portable or autonomous sensor systems is often lower than 50kHz with ADC requiring about 8 to 10 bits resolution, but the consumed power must be very low: few μW or a FOM = P/(2ENoBfsampl) lo