Pohang University of Science and Technology

Abstract This work presents a 0.87pJ/b, 17Gb/s/pin parallel receiver with local DQS recovery and a dual-DQS tree for reduced clock power and mitigated power supply-induced jitter (PSIJ). The local DQS recovery time-multi

*Equally Credited Authors Fully homomorphic encryption (FHE) has been gaining significant attention as a privacypreserving solution for emerging server systems with critical information, which allows the server to perform

superconducting qubits foresee reaching the next milestones of the exponentially growing number of qubits. The promises in the scalability present opportunities in integrated control electronics operating at 4K stage in

Samsung Electronics, Hwaseong, Korea SSC DECS input, the resulting clock and data paths are equally matched and the impact of the RX SN on the RX performance is minimized. In a conventional RX the sampling clock is gener

There has been increasing demand for a low-power wearable device to perform longterm ambulatory monitoring of electrocardiogram (ECG). However, for a wearable device to be a convenient continuous recording system in one’

Physically unclonable functions (PUFs) have been actively investigated as a promising solution for low-cost secure authentication in Internet of Things (IoT) applications. A PUF should generate unique challenge-response

various internal voltages. Since it consumes static power in standby modes, it plays an important role in energy management of battery-limited applications. The bandgap reference (BGR) has been a widely used approach sin

On-chip true random number generators (TRNG) have been gaining attention as an important component for building secure systems [1]. CMOS TRNGs typically exploit device-level noise, such as thermal or flicker noise to gen

wearable and implantable technologies, there has been growing demand on development of key enabling circuits for ultra-low-power sensor interface SoCs. As a reference-frequency generation block for clock management of th

Samsung Electronics, Yongin, Korea 1 2 Point-to-point data transmission with clock-embedded signaling (CES) has been generally adopted in intra-panel interfaces, which need to support fine resolution, high frame rate, an

University of Michigan, Ann Arbor, MI 1 2 Recent advances in nW-level wireless sensor nodes have created opportunities in emerging applications such as bio-implantable telemetry, smart healthcare, and environmental monit

sense-amplifier load in the receiver. In this work, IDRV and IPE were set to 95μA and 45μA, respectively. For the receiver equalization, the PMOS diode in the sense-amplifier load is modified to form an active inductor c

University of Michigan, Ann Arbor, MI 1 2 Emerging demands on ultra-low-power wireless sensor platform have presented challenges for nano-watt design of various circuit components. Clock management unit, as an essential

In the design of a fractional-N PLL, the trade-off between in-band VCO noise and ΔΣ quantization noise constrains the choice of loop bandwidth. Various circuit schemes have been proposed to relax such constrains with noi

since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference be