ISSCC 2026
Session 27
Clocking & PLLs
A 77GHz 8-bit CMOS Phase Shifter Adopting a Nested-Vector-Based Error Correction with 0.33°/0.07dB RMS-Error for MIMO Radar Applications
Abstract In this paper, we present a 77GHz 8-bit nested vector-sum phase shifter in 28nm CMOS. The architecture performs vector modulation by splitting a single outer vector into two inner vectors generated by a two-stag
ISSCC 2026
Session 25
Hardware Security
A PVT Variation- and Attack-Tolerant Metastability-Based TRNG Using Binary Search in 2nm
Abstract This work presents a single source, metastability-based TRNG using binary search with offset-tunable comparator. The proposed TRNG operates without warm-up time and is robust against low-frequency noise, PVT var
ISSCC 2026
Session 24
Sensors
A 28nm CMOS 1-Chip In-Pixel Memory Backplane Circuit with Pixel-Level Sensing and Compensation for 6652-PPI MicroLED AR Glasses
6652-PPI microLED AR display. Pixel-level sensing with pBIST enables accurate calibration and compensation of current variation. The 2.7µm-pitch array integrates an 8b shifter with MSB latch for PWM. System techniques in
ISSCC 2026
Session 21
RF & Wireless
A 0.6V 625um2 Fully Stacked RC-Based Temperature Sensor Using Low TCR Metal Resistor Achieving 0.017nJ·%2-Accuracy FoM in 2nm Gate-All-Around Process
Abstract The proposed RC-based temperature sensor, fabricated on a 2nm gate-all-around process, minimizes silicon area by fully stacking low temperature coefficient of resistance (TCR) metal resistors and a ring-oscillat
ISSCC 2026
Session 20
RF & Wireless
A High Back-off Efficiency Unequal-Stacked Doherty Power Amplifier Achieving 16.7dBm Pavg in a 22nm FDSOI CMOS Technology for 5G FR2 Applications
Abstract This paper proposes an unequal-stacked Doherty power amplifier. The proposed Doherty structure consists of a common-source topology for the carrier amplifier and an N-stacked topology for the peaking amplifier w
ISSCC 2025
Session 1
Plenary
AI Revolution Driven by Memory Technology Innovation Jaihyuk Song
1.0 Introduction The memory industry is facing unprecedented challenges as it enters the AI era. The “memory wall” phenomenon, which impedes the speed of system improvements and the evolution of AI algorithms, is intensi
ISSCC 2022
Session 28
Memory
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter
SK hynix, Icheon, Korea 3 Korea Aerospace Research Institute, Daejeon, Korea 4 KAIST, Daejeon, Korea 1 2 *Equally Credited Authors (ECAs) With the increasing demand for low-power, high-speed DRAMs, LPDDR5 featuring a spe
ISSCC 2022
Session 13
Digital Circuits
A 0.65V 1316µm2 Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving 0.16nJ·%2-Accuracy FoM in 5nm FinFET CMOS
performance of SoCs, which is rapidly increasing overall chip temperature. As a result, dynamic thermal management (DTM) using a number of temperature sensors is essential. For accurate temperature measurement, the senso
ISSCC 2022
Session 13
Digital Circuits
Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC
In mobile SoC, clock sources such as PLLs, are expensive resources both in terms of area and power, and they are commonly shared by multiple clock consumers. To that end, the latest SoCs hold tens of PLLs and hundreds of
ISSCC 2018
Session 7
Clocking & PLLs
A 0.02mm2 Fully Synthesizable Period-Jitter Sensor Using Stochastic TDC Without Reference Clock and Calibration in 10nm CMOS Technology
becomes challenging. To effectively manage the tight jitter performance required by an SoC, the clock quality should be directly evaluated at every point where the clock is used in the SoC. In previous work [1-3], on-chi