ISSCC 2026
Session 13
Other
A Nonintuitively Frequency-Staggered Wideband mm-Wave Low-Noise Amplifier
Abstract An algorithmic topology optimization framework is presented to autonomously synthesize nonintuitive, multilayered wideband mm-Wave LNAs with arbitrary stage count. Cooptimization of actives and passives directly
ISSCC 2026
Session 13
Other
An Inverse-Designed Passively Coupled N-Path Filter with gm-Boosted Active HBT Switches
Abstract A 0.8-to-2.6GHz N-path filter with gm-boosted HBT switches and inverse-designed nonresonant passive networks is presented to enhance dynamic range and tunability of passively coupled higher-order N-path filters.
ISSCC 2024
Session 5
Wireless
A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS
Conventional wireless receivers employing a heterodyne/homodyne architecture or Npath filter often result in a significantly higher area and power overhead owing to the requirement of LO generation and distribution at high
ISSCC 2023
Session 14
Digital Circuits
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur
University of Waterloo, Waterloo, Canada 1 2 Ring-oscillator (RO)-based injection-locked phase-locked loops (IL-PLLs) and multiplying delay-locked loops (MDLLs) are promising candidates for low-cost, highperformance cloc
ISSCC 2022
Session 10
Data Converters
A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology
High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-do
ISSCC 2021
Session 29
Digital Circuits
A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur
Inphi, Santa Clara, CA 1 2 Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scalingfriendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has bee
ISSCC 2021
Session 26
RF & Wireless
A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency
Enhancing PA efficiency in the power back-off (PBO) region has become an important design objective due to the high peak-to-average power-ratio (PAPR) modulation in modern communications. Recently, a voltage-mode subharm
ISSCC 2021
Session 19
Wireline I/O
Optical Phased-Array FMCW LiDAR with On-Chip Calibration
Light detection and ranging (lidar) sensors provide high resolution and high accuracy for diverse applications such as autonomous vehicles and three-dimensional imagers. Over the past few years, there has been significan
ISSCC 2020
Session 16
Data Converters
A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS
A low-power, wide-bandwidth, and high-dynamic-range (DR) ADC is one of the critical building blocks in a wireless receiver design, in which a continuous-time delta-sigma modulator (CT DSM) has become a popular choice. Ho
ISSCC 2020
Session 10
RF & Wireless
A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation
A key aspect of 5G systems is supporting multiband and multistandard applications. Depending on operating conditions, this requires high in-band dynamic range and/or low noise floor at specific out-of-band (OOB) frequenc
ISSCC 2019
Session 4
Power Management
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency
Modern wireless communication systems often utilize spectrum-efficient modulation schemes for higher data throughput, given the finite bandwidth. This type of modulation schemes, such as Orthogonal Frequency Division Multi
ISSCC 2018
Session 26
RF & Wireless
A 13th-Order CMOS Reconfigurable RF BPF with Adjustable Transmission Zeros for SAW-Less SDR Receivers
Current cellular receivers often employ acoustic filters (SAW or BAW) for each communication band due to their high selectivity, low insertion loss, and small formfactor. The need to support multiple communication bands,
ISSCC 2018
Session 25
Wireline I/O
A Fractional-N Digital PLL with Background-DitherNoise-Cancellation Loop Achieving <-62.5dBc WorstCase Near-Carrier Fractional Spurs in 65nm CMOS
Fractional-N digital phase-locked loops (DPLLs) are highly reconfigurable, scalable, and useful for synthesizing clocks with fine frequency resolution for modem RF, mixed-signal and digital VLSI systems. One critical des
ISSCC 2018
Session 22
Data Converters
A 16b 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 Within DC-to-6GHz Tunable Passbands
The agile allocation of signal bands over RF frequencies and high in-band spectral purity (both SFDR and NSD) can enable higher-order modulation in highthroughput flexible wireless/wireline transmitters, where signals ar
ISSCC 2018
Session 15
RF & Wireless
A Digital Frequency Synthesizer with Dither-Assisted Pulling Mitigation for Simultaneous DCO and Reference Path Coupling
Injection pulling on frequency synthesizers has become a critical design challenge for high-performance wireless transceivers, especially in highly integrated multiradio platforms, imposing stringent constraints on syste
ISSCC 2017
Session 15
Other
A 1024-Element Scalable Optical Phased Array in 0.18µm SOI CMOS
Self-driving cars, drones, and other autonomous systems rely on a number of sensors such as cameras, radars, and ultrasonic detectors to observe their surrounding environments. Light detection and ranging (lidar), where
ISSCC 2016
Session 27
Data Converters
A 12b 2GS/s Dual-Rate Hybrid DAC with Pulsed Timing-Error Pre-Distortion and In-Band Noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS
A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its
ISSCC 2016
Session 10
Wireline I/O
A Digital PLL with Feedforward Multi-Tone Spur Cancelation Loop Achieving <-73dBc Fractional Spur and <-110dBc Reference Spur in 65nm CMOS
A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL
ISSCC 2015
Session 19
Wireless
Reconfigurable SDR Receiver with Enhanced FrontEnd Frequency Selectivity Suitable for Intra-Band and Inter-Band Carrier Aggregation
The demand for increased wireless data throughput in future wireless communication and the lack of available wide contiguous frequency bands inspire the concept of aggregating multiple frequency bands in a SoftwareDefine
ISSCC 2010
Session 2
RF & Wireless
A True Time-Delay-Based Bandpass Multi-Beam Array at mm-Waves Supporting Instantaneously Wide Bandwidths
The phased array is a common technique where multiple spaced antennas electronically form and scan narrow electromagnetic beams to achieve spatial selectivity. These arrays are also referred to as steering arrays. On the
ISSCC 2009
Session 22
RF & Wireless
A 0.13µm CMOS Power Amplifier with Ultra-Wide Instantaneous Bandwidth for Imaging Applications
The increased interest in Ultra-WideBand (UWB) impulse-based systems for high-resolution imaging applications [1] has created a demand for mediumpower linear amplifiers capable of transmitting such signals (FCC limits pe
ISSCC 2008
Session 6
RF & Wireless
A CMOS UWB Camera with 7×7 Simultaneous Active Pixels
Ultra-wideband (UWB) imaging systems achieve high depth resolution. UWB timed arrays use a collection of spaced antennas to achieve azimuth selectivity as well [1]. The recent trend in realization of integrated beam-form