ISSCC 2024
Session 12
RF & Wireless
A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency
Louis, St. Louis, MO 1 2 Correlators are fundamental building blocks in radar/communication signal processing and analog-to-information (A-to-I) applications such as spectrum sensing [1]. Typically, correlation, which is
ISSCC 2022
Session 25
Data Converters
A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS
Demands for battery-powered consumer electronics have driven the evolution of powerefficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery
ISSCC 2021
Session 14
mm-Wave
A 26GHz Full-Duplex Circulator Receiver with 53dB/400MHz (40dB/800MHz) Self-Interference Cancellation for mm-Wave Repeaters
Reduction in base-station deployment costs while increasing coverage has motivated Integrated Access and Backhaul (IAB) nodes in mm-wave 5G NR (Fig. 14.3.1). Similarly, high path loss due to shadowing and limited outdoor
ISSCC 2020
Session 26
Medical & Bio
A 20µW Heartbeat Detection System-on-Chip Powered by Human Body Heat for Self-Sustaining Wearable Healthcare
*Equally-Credited Authors (ECAs) Wearable devices are expanding beyond consumer and entertainment applications, including continuous monitoring of vital signs for medical diagnostics, due to extended ambulatory measureme
ISSCC 2018
Session 8
Wireless
A 960pW Co-Integrated-Antenna Wireless Energy Harvester for WiFi Backchannel Wireless Powering
power sensors can enable perpetually powered sensors for several monitoring and asset-tracking IoT applications. Small form factor is often desirable to ensure unobtrusive sensors. However, typical 2.4GHz WiFi output pow
ISSCC 2018
Session 26
RF & Wireless
A 0.55-to-0.9GHz 2.7dB NF Full-Duplex HybridCoupler Circulator with 56MHz 40dB TX SI Suppression
Simultaneous transmit-and-receive (STAR) radios enable higher spectrum efficiency and dynamic spectrum access. The integration of a shared antenna interface is attractive for small system formfactor and MIMO channel esti
ISSCC 2018
Session 14
Data Converters
A 50MHz-BW Continuous-Time ΔΣ ADC with Dynamic Error Correction Achieving 79.8dB SNDR and 95.2dB SFDR
MediaTek, Woburn, MA 1 2 Continuous-time ΔΣ modulators (CTDSMs) are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requi
ISSCC 2017
Session 29
Wireline I/O
A 16Gb/s 3.6pJ/b Wireline Transceiver with Phase Domain Equalization Scheme: Integrated Pulse Width Modulation (iPWM) in 65nm CMOS
Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FF
ISSCC 2016
Session 21
Wireless
A 1.2cm2 2.4GHz Self-Oscillating RectifierAntenna Achieving -34.5dBm Sensitivity for Wirelessly Powered Sensors
Ubiquitous Internet-of-Everything (IoE) applications require low-cost, miniature sensors with long lifetimes. Wirelessly-powered ICs that harvest energy from an RF beacon or from existing wireless signals can address cha
ISSCC 2016
Session 2
RF & Wireless
A Scalable 28GHz Coupled-PLL in 65nm CMOS with Single-Wire Synchronization for LargeScale 5G mm-Wave Arrays
Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improvements in network capacity [1,2]. Practical conside
ISSCC 2014
Session 9
Wireless
A 1.3mW 0.6V WBAN-Compatible Sub-Sampling PSK Receiver in 65nm CMOS
Fudan University, Shanghai, China 1 2 The release of the IEEE802.15.6 standard has led to increased interest in lowpower technologies for wireless body-area-networks (WBAN). The power dissipation, supply voltage, and IC
ISSCC 2014
Session 2
Wireline I/O
A 0.25pJ/b 0.7V 16Gb/s 3-Tap Decision-Feedback Equalizer in 65nm CMOS
Texas A&M University, College Station, TX, 3 Fudan University, Shanghai, China 1 2 Supply-voltage scaling has become one of the most effective methods to improve the energy efficiency of power-constrained systems, motiva
ISSCC 2012
Session 27
Data Converters
A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V Two-Step Pipelined ADC in 0.13µm CMOS
National Semiconductor, Santa Clara, CA which may be done simply by changing the gain combination in the two cascaded gain stages. Such optimization may lead to further reduction in power consumption and also allow for l
ISSCC 2012
Session 27
Data Converters
A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth Highly Digital Time-to-Digital Converter Using Switched Ring Oscillators
Time-to-digital converters (TDCs) were historically used in laser range-finding, automatic test equipment, and timing jitter measurements, but recent developments in the design of high-resolution TDCs have paved the way
ISSCC 2011
Session 5
Clocking & PLLs
A 0.4-to-3GHz Digital PLL with Supply-Noise Cancellation Using Deterministic Background Calibration
viable alternative to classical charge-pump analog PLLs [1-4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processe
ISSCC 2011
Session 27
Data Converters
A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bidirectional Single-Slope Quantizer
The aspirations for power efficient ADCs have led to many improvements in this area. In delta-sigma modulators, techniques such as VCO-based quantizer [1, 2] and time-domain quantization [3] have been proposed to enhance
ISSCC 2011
Session 25
Wireline I/O
A TDC-less 7mW 2.5Gb/s Digital CDR with Linear Loop Dynamics and Offset-Free Data Recovery
A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phaselocked loop (PLL) wherein a passive lead-lag analog loop filter is
ISSCC 2011
Session 25
Wireline I/O
A 0.5-to-2.5Gb/s Reference-less Half-Rate Digital CDR with Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate
ISSCC 2010
Session 16
Data Converters
A 1.4V Signal Swing Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing Opamp
Scaling in CMOS technologies has made the application of traditional opamp topologies increasingly difficult. In the face of decreasing voltage headroom and intrinsic device gain, designers have employed techniques such
ISSCC 2008
Session 30
Data Converters
An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain
Finite opamp gain and output swing are two limitations for precision analog circuits. These limitations are especially serious at lower supply voltages where limited headroom prevents the use of cascode devices to improv