Seoul National University

Abstract A low-power (0.292pJ/b), high-bandwidth (56Gb/s/wire) single-ended capacitively driven simultaneous bi-directional (CD-SBD) TRX with PVT tolerance is proposed. Capacitive driving reduces power and self-interfere

KAIST, Daejeon, Korea 3 Kyung Hee University, Yongin, Korea 1 2 *Equally Credited Authors (ECAs) With the advent of the generative AI era, high-bandwidth memory (HBM) has emerged as an irreplaceable solution that can pro

Columbia University, New York, NY 1 (Fig. 37.7.3, top). The butterfly unit receives 8 real inputs and 8 imaginary inputs in signand-magnitude format, through an input router switching between them. When real (imaginary)

KAIST, Daejeon, Korea 1 2 *Equally Credited Authors (ECAs) The explosive expansion of generative AI, in various industries, has led to a surge in demand for high-bandwidth memory (HBM) devices that feature thousands of D

Speech enhancement (SE) is a task to improve voice quality and intelligibility by removing noise from the audio, which is widely adopted in hearing assistive devices. Hearing aids are generally worn in or behind the ear,

Advances in virtual reality, artificial intelligence, and big data have increased demand for high-bandwidth memory. Accordingly, pre-fetch sizes have also increased with DRAM generations, meaning an increased number of g

*Equally Credited Authors (ECAs) Recent works on mobile deep-learning processors have presented designs that exploit sparsity [2, 3], which is commonly found in various neural networks. However, due to the shift in the m

a silicon interposer technology to increase the number of I/O pins. Interfaces with the silicon interposer provide a higher throughput (Gb/s/µm) than other packaging technologies due to the high channel density. To incre

Continuous-rate referenceless clock and data recovery (CDR) circuits are capable of operating over a wide range of data rates in multiple standards. To achieve wide-range operation without an external reference clock, se

Digital low-dropout regulators (DLDOs) are commonly used in low-power systemon-chips (SoCs) because of their low-voltage operation and fast transient response via the digital control of a power gate. However, the digital

paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced timing budget. However, phase errors between multiphase clocks, due to device mismatch, degrade

Samsung Electronics, Hwaseong, Korea 1 2 Demand for DC-DC voltage conversion from a 48V input has been on the rise due to proliferation of server and automotive applications with a 48V intermediate bus and 48V batteries,

High-resolution read-out integrated circuits (ROICs) are often used in DC measurement systems such as bridge transducers. Since these typically output small-amplitude signals with a bandwidth of a few hertz, a highly lin

1.3 shows the circuit implementation of the low-power PI used in the phase DAC. The PI stage consists of two complementary parts, each interpolating between the rising or falling edges of the two input clocks, respective

tablet PCs and home appliances that have touch-screen panels (TSPs) larger than 10 inches. However, there are many sources of noise that affect touch detection, and some of these noise sources, such as charger noise, sig

digital TVs and also in other video applications. A low integrated jitter is required for good display quality. However, an extremely low input frequency coming from the horizontal synchronization signal (HSYNC) makes it

As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since