Intel

work demonstrates a UCIe-S compliant die-to-die PHY at 48Gb/s/lane across 16 lanes, achieving 1.24Tb/s/mm shoreline BW density over a 30mm organic package at 1.2pJ/b, extendable to 56GT/s (1.13pJ/b). Circuit innovations

Processing Unit (Intel IPU) E2000 is Intel’s first ASIC IPU device, a 200G product co-designed with Google and in production as of 2022. It features a rich packet processing pipeline, RDMA and storage capability includin

(SoC) to provide information about die temperature for thermal protection or performance optimization. To enable the deployment of multiple sensors in an SoC, the power and size of such sensors has been steadily reduced.

Proximity communication offers the convenience of a connector-less high-speed interface using energy-efficient mixed-signal transceivers [1-4]. Such interfaces are attractive for ultra-thin handheld/mobile devices with z

In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chi

Mobile SoC designs demand a low-power clocking system to maximize battery life. The host PLL is critical since it must remain enabled to support always-on, always-connected operation. In addition, the host PLL should off

Thermal sensors are used in modern microprocessors to provide information for: 1) throttling at the maximum temperature of operation, and 2) fan regulation at temperatures down to 50°C. Today’s microprocessors are therma

1.0 Introduction Moore’s Law will continue to hold throughout the decade, allowing us to double transistor integration capacity while reducing power, thus providing an abundance of transistors needed to realize novel arc

System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC h

random threshold voltage (Vth) fluctuations is crucial in process optimization and yield learning, particularly for matching critical transistors such as SRAMs, sense amplifiers, differential amplifiers, etc. Traditional

high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-VT low-power (LP) CMOS proces

Nehalem is a family of next-generation IA processors for mobile, desktop and server segments implemented in 45nm high-κ metal-gate CMOS [1]. The family features a new system architecture, significantly enhanced Core arch

transceivers. To offset the oscillator frequency from the PA output frequency, SSB mixing or division-by-2 is typically used [1]. However, the first might require additional filtering to remove mixing spurs and the latte

cores over its predecessor [2], from 2 to 4. It also adds a system interface that is roughly as large as two cores, including six QuickPath interconnects and four FBDIMM channels. This 3× increase in logic circuits per s

11n/WiMAX receivers (20 to 2.5MHz per I/Q) is presented. The intent is to replace complex analog baseband circuits with a combination of tunable one-pole filter, anti-alias filter and coarse VGA (Fig. 27.5.1) [1]. Blocke